A wide frequency range delay line for fast-locking and low power delay-locked-loops

Estebsari, Motahhareh; Gholami, Mohammad; Ghahramanpour, Mohammad Javad

doi:10.1007/s10470-016-0824-z

Cited by 8 publications

(7 citation statements)

References 14 publications

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“…When input signal is injected to the circuit, this cross couple pair is converted to a positive feedback, and it consequently increases the signal transient speed. In fact, by applying this method, signal would have higher speed transient edge . From the other side, M1 and M4 in parallel with M2 and M3 are used while all of them are in the triode region and increase driving capability.…”

Section: Wide Range Delay Locked Loopmentioning

confidence: 99%

“…In fact, by applying this method, signal would have higher speed transient edge. 2 From the other side, M1 and M4 in parallel with M2 and M3 are used while all of them are in the triode region and increase driving capability. Control voltage which is actually in the output of charge pump and loop filter is injected into NMOS transistors in transmission gates, and this changes amount of delay.…”

Section: Proposed Voltage Controlled Delay Linementioning

confidence: 99%

“…Lock range can increase in a VCDL through increasing delay cells. In other words, delay range implies frequency range which a DLL can lock . The small and random variations in output signal are called jitter.…”

Section: Introductionmentioning

confidence: 99%

“…In other words, delay range implies frequency range which a DLL can lock. 2 The small and random variations in output signal are called jitter. DLLs show better jitter performance in comparison with PLLs.…”

mentioning

confidence: 99%

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A wide range delay locked loop for low power and low jitter applications

Estebsari

Gholami

Ghahramanpour

2017

Circuit Theory & Apps

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Summary In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.

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Section: Wide Range Delay Locked Loopmentioning

confidence: 99%

Section: Proposed Voltage Controlled Delay Linementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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A wide range delay locked loop for low power and low jitter applications

Estebsari

Gholami

Ghahramanpour

2017

Circuit Theory & Apps

Self Cite

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“…But operating range still is not wide-band. 9,10 Forward body bias reduces the threshold voltage in which current of transistors changes in whole controlled voltage range. So, tuning range of delay cell increases.…”

Section: Introductionmentioning

confidence: 99%

Low‐power and wide‐band delay‐locked loop with switching delay line

Rezaeian

Ardeshir

Gholami

2018

Circuit Theory & Apps

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A low-power and wide-band delay-locked loop (DLL) is presented. Switching the delay line is used to enhance the input frequency range of the DLL. First delay line with short delay times is designed for high frequencies, and second delay line with long delay times is designed for low frequencies. Also, a switching circuit is used to control the delay lines. Proposed delay lines give delay range 0.5 to 34 nanoseconds in which DLL can operate input frequency range of 30 MHz to 2 GHz. This DLL has been simulated in 0.18-μm CMOS technology. The simulated root-mean-square and peak-to-peak jitters are 3.12 and 11.03 picoseconds at 2 GHz, respectively. The power dissipation at 2 GHz is 3.24 mW for a supply voltage of 1.8 V.

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