A Wide-Bandwidth 2.4 GHz ISM Band Fractional-$N$ PLL With Adaptive Phase Noise Cancellation

Swaminathan, A.; Wang, K.J.; Galton, I.

doi:10.1109/jssc.2007.908763

Cited by 100 publications

(21 citation statements)

References 14 publications

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“…Synchronizing the divider output to the VCO signal by a flip-flop can reduce MDDD [1]. However, care must be taken to avoid metastability; the attendant circuitry could result in high power consumption [1], [2], [32]. Note that, if the divider is realized as a chain of 2/3 cells, the "mod" signal in the first (high frequency) 2/3 cell stage can be used as a synchronized divider output.…”

Section: B Modulus-dependent Divider Delaymentioning

confidence: 99%

“…Phase noise cancellation techniques have been reported to cancel the quantization noise that would have been otherwise suppressed by a narrow PLL bandwidth [1], [2], [4], [6], [32], [33], [37]. They digitally calculate the DDSM quantization noise and inject a compensation charge into the loop filter using a digital-to-analog converter (DAC).…”

Section: Wide-bandwidth Frequency Synthesismentioning

confidence: 99%

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Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

Pamarti

2009

IEEE Trans. Circuits Syst. II

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Section: B Modulus-dependent Divider Delaymentioning

confidence: 99%

Section: Wide-bandwidth Frequency Synthesismentioning

confidence: 99%

Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

Pamarti

2009

IEEE Trans. Circuits Syst. II

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“…Therefore, it is prospective to achieve better phase noise performance. In recent years, many researches are directed against quantization noise reduction on PLLs [1][2][3][4][5][6] and aim to obtain a good performance of PLL. Literature [1] uses a multiphase reference signal and a circulator to increase the operating frequency of the M ∑ Δ , then, shifts the quantization noise to higher frequency and utilizes the low-pass characteristic of the PLL to suppress it.…”

Section: Introductionmentioning

confidence: 99%

“…Literature [2] uses a three-phase sample-hold-reset loop filter to achieve better phase frequency detector and charge pump (PFD-CP) linearity, and implements an extended linear-range phase generation (ψ-gen) logic to minimize phase noise and spur. The authors estimate the quantization noise and using a current digital-to-analog converter (DAC) to cancel the quantization noise at the charge pump output, but it requires additional power consumption and calibration time [3]. Literature [4] presents a finite impulse response (FIR) embedded noise filtering method which reduces the out-of-band phase noise and improves short-term jitter performance, but this method needs multi-input charge pump and many PFDs and MMDs.…”

Section: Introductionmentioning

confidence: 99%

A 2.4-GHz fractional-N frequency synthesizer with noise filtering technique for wireless application

Huang

Lai

2015

2015 International Symposium on Next-Generation Electronics (ISNE)

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A hybrid fractional-N frequency synthesizer with noise filtering technique for wireless application is implemented with TSMC 0.18 µm CMOS process. In order to reduce the effects of high order delta-sigma modulator ( M ∑ Δ ), and suppress the out-of-band quantization noise, a noise filter is adopted. An integer-N phase-locked loop acts as the noise filter in the feedback path of a fractional-N frequency synthesizer. With supply voltages of 0.9 V for analog circuits and 1.8 V for digital circuits, measured results achieve that output frequency of VCO is tunable from 2.30 to 2.52 GHz, corresponding to 9.1%, a frequency synthesizer phase noise of -113.51 dBc/Hz at 1 MHz offset from carrier frequency of 2.41 GHz, and a overall power consumption of 20 mW. Including pads, the total chip area occupies 0.922 (0.94 × 0.98) mm 2 .

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“…In traditional fractional-N PLL, spurious level depends on loop bandwidth and sigma-delta order. Compensations of this type of spurious exist [5][6], but are neither power nor area friendly. The proposed architecture is dedicated for FDSOI technology using back-gate biasing opportunity to reduce the phase noise.…”

Section: Introductionmentioning

confidence: 99%

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

et al. 2015

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MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide (BOx). Called ultra thin body and buried oxide (UTBB) transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator (VCO) based on a ring oscillator (RO) designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about --94 dBc/Hz@1 MHz.

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A Wide-Bandwidth 2.4 GHz ISM Band Fractional-$N$ PLL With Adaptive Phase Noise Cancellation

Cited by 100 publications

References 14 publications

Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

A 2.4-GHz fractional-N frequency synthesizer with noise filtering technique for wireless application

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

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