A VLSI sorting image sensor: global massively parallel intensity-to-time processing for low-latency adaptive vision

Simultaneous sensing, readout, and classification on an intensity‐ranking image sensor

“…Here, we extend the idea of using time to represent light intensities, by combining it with address‐event representation (AER). Address‐event representation has been described in a number of papers, see eg, Leñero‐Bardallo et al and Brajovic and Kanade, and recently, computer vision methods for AER sensors (“event‐based vision”) have attracted interest in the research community (eg, Gallego et al and Mueggler et al) as well as for commercial implementations. The idea behind AER is to output the address of “events” as they occur in the image.…”

A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion

“…One of the first imagers based on direct integration-time measurement was the MAPP2200 sensor developed by Forcheimer et al [8]. Later, Brajovic [9] developed a twist on the direct timer architecture by assigning indices to pixels based on their relative switching times. This design allowed inherent gain control and histogram-based quantization, but was limited by its use of analog values to represent global quantities.…”

Modular Design of High-Throughput, Low-Latency Sorting Units

“…Sorting is an important operation in a wide range of applications including data mining, databases [7,19,31], digital signal processing [47,48], network processing, communication switching systems [4,58], scientific computing [15], searching, scheduling [51], pattern recognition, robotics [10], image and video processing [11,12,17,49], and high-energy physics (HEP) [23,55]. For applications that require very high-speed sorting, hardware sorting units are often implemented using either ASICs or FPGAs to meet performance requirements [13,28,31,33,38,41,49].…”