A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion

McIlrath, L.

doi:10.1109/4.918924

Cited by 131 publications

(59 citation statements)

References 13 publications

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“…In previous works, decimation was performed at the chip level [7], [8]. But this entails a high bit rate at the pixel output, which limits the bit resolution, frame rate, and window size.…”

Section: Decimator Designmentioning

confidence: 99%

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Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

Mahmoodi

Joseph

2008

2008 51st Midwest Symposium on Circuits and Systems

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Abstract-Area and power optimization of a first-order deltasigma analog-to-digital converter (ADC) for pixel-level data conversion is presented. The ADC is designed for use in a verticallyintegrated logarithmic CMOS image sensor. A switched-capacitor modulator with minimum area has been employed. Unlike other similar structures, the decimation is performed inside the pixel to decrease its output bit rate. The proposed ADC has an area of 32 × 31 µm 2 and consumes 680 nW of power to achieve 80 dB of signal-to-noise ratio with a frame rate of 50 Hz. The circuit was implemented in 0.18 µm CMOS technology with a die area of 2 mm 2 and has been sent for fabrication.I. INTRODUCTION Dynamic range (DR) and signal-to-noise ratio (SNR) are two major specifications of CMOS image sensors [1]. High DR and SNR are demanded by several applications. Linear sensors achieve a high SNR by photocurrent integration but have a low DR. While the human eye has a DR of over 100 dB, linear sensors capture only 70 dB without saturation. Time-based linear sensors have a higher DR but need a long integration time, which limits the frame rate [2]. Logarithmic sensors employ a transistor in subthreshold mode to convert the photodiode current in logarithmic scale to a voltage to achieve a DR of over 160 dB [3]. However, these sensors suffer from high fixed-pattern noise (FPN) and low SNR. It has been shown that FPN can be effectively reduced using a calibration method [3]. Hence, having low SNR remains as the main drawback. A delta-sigma analog-to-digital converter (ADC) for pixel-level data conversion can achieve high SNR to improve the SNR of logarithmic sensors.Pixel-level data conversion has several advantages. Digital pixels can reduce the readout noise to achieve a higher SNR. Also, since the ADCs are working at very low speed in the subthreshold region, they consume very low power. In addition, the readout speed is not as limited by bus capacitance so higher frame rates may be possible. The main issue with digital pixels is the large pixel size [1].In [4], different pixel designs for high DR and SNR have been compared. The authors conclude that with the present methods, if not impossible, it would be difficult to achieve high DR and SNR with a reasonable pixel size. But recent interest in vertically-integrated image sensors means more area will be available inside the pixel to process the sensitive signal of the photodiode [4], [5]. In [5], an image sensor has been designed for infrared applications using vertical integration. While its

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“…In previous works, decimation was performed at the chip level [7], [8]. But this entails a high bit rate at the pixel output, which limits the bit resolution, frame rate, and window size.…”

Section: Decimator Designmentioning

confidence: 99%

“…Others have tried to improve this method. McIlrath used the pixel structure as a free running oscillator to implement the modulator [8]. She used a recursive method in the decimator at the chip level, to decrease the required bit rate, but a high SNR was not achieved due to a limited oversampling ratio (OSR).…”

mentioning

confidence: 99%

Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

Mahmoodi

Joseph

2008

2008 51st Midwest Symposium on Circuits and Systems

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“…However, SAR ADC tends to be interfered in a noisy environment, because it performs the conversion for a single sample of the input voltage. Additionally, traditional low-order AEÁ ADC without dithering techniques is also not suitable for DC signals because of pattern noise issues [5]. In order to utilize the signal-average advantage of AEÁ techniques, a 12-bit second-order incremental AEÁ ADC which is also described in [6] is adopted for the presented chip.…”

Section: Introductionmentioning

confidence: 99%

A multi-cell battery pack monitoring chip based on 0.35-µm BCD technology for electric vehicles

Wang

Zhang

et al. 2015

IEICE Electron. Express

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This letter presents a multi-cell battery pack monitoring chip for electric vehicles (EVs). A multiplexer based on p-and n-type lateral doublediffused MOS (LDMOS) transistors is proposed to select the battery voltage in a battery pack with up to 12 series-connected battery cells. Measuring of the cell voltages is realized by a 12-bit incremental ΣΔ analog-to-digital converter (ADC) with offset cancellation. Fabricated in a 0.35-µm Bipolar-CMOS-DMOS (BCD) technology, measurement results show that an absolute conversion error of less than 3 mV is obtained. The conversion time for each cell is less than 600 µs under a 1-MHz clock signal generated by an internal oscillator. The chip area is 4 × 3.8 mm 2 and the current consumption is 510 µA in measuring mode, resulting in a operation power loss of 25.5 mW under a 50-V power supply.

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“…The RD19 development program was then started at CERN to develop pixel detectors suited for the LHC experiments. The successors of the LAA chip were the OmegaD [41], the Omega2 [42] and the Omega3 [43].…”

Section: Photon Counting Hybrid Pixel Detectorsmentioning

confidence: 99%

“…In an integrating imaging system there is a clear separation between the time used to collect the charge resulting from the photon interactions and the time when this accumulated charge is read from the pixels and processed. This feature is exploited in both column-level [35,36] and pixel-level [37,38,39,40,41,42,43] ADCs to operate, respectively, all columns or all pixels in parallel. As a result, slower ADCs than those in the chip-level approach can be used.…”

Section: Pixel-level Analog-to-digital Convertersmentioning

confidence: 99%

Spectroscopic quantum imaging using pixel-level ADCS in semiconductor-based hyrid pixel detectors

Bello¹

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A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion

Cited by 131 publications

References 13 publications

Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

Pixel-level delta-sigma ADC with optimized area and power for vertically-integrated image sensors

A multi-cell battery pack monitoring chip based on 0.35-µm BCD technology for electric vehicles

Spectroscopic quantum imaging using pixel-level ADCS in semiconductor-based hyrid pixel detectors

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