A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer

A new technique for the stabilization of local oscillators by the way of frequency synthesis is presented. A combination of both a PLL and a DLL in a novel frequency synthesizer architecture overcomes the drawback of PLL stability, while avoiding the classical DLL out-of-band spurious. Therefore, the Mixed P/DLL synthesizer can exhibit very wideband and, consequently, can dramatically reduce the local oscillator phase noise and the synthesizer settling time. Dynamic performances of an unstable PLL are then observed, while the system stability is guaranteed by the DLL first order loop behavior. A 130nm CMOS experimental demonstrator is presented, able to synthetize local oscillator form 1 to 3.5GHz, with settling time as low as 1.2µs.

show abstract

“…Delay Locked Loops (DLL) offers another option for frequency generation [3,4]. Indeed, while close to the PLL topology as depicted in Fig.…”

Section: B the Delay Locked Loopmentioning

confidence: 98%

The P/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation

Deval

Peslouan

Taris

et al. 2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Unfortunately, such a large band could only be reached with ring oscillator topologies [6], but the poor phase noise of the structure is not suitable for the present requirements. The Delay Locked Loop (DLL) [7] architecture is presented in the right part of the Figure 1. It is composed by a phase frequency detector, a charge-pump and loop filter and there is a Voltage Controlled Delay Line (VCDL) instead of the VCO.…”

Section: Introductionmentioning

confidence: 99%

A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture

Peslouan

Majek

Taris

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of the both architecture and more particular to the non-accumulation of random timing jitter. On the other hand, such a methodology could relax constraints on the loop filter and it would then be possible to increase the architecture bandwidth without taking care of stability drawbacks. By the way, the settling time could be largely improved.

show abstract

“…Unfortunately, it can not reach the required phase noise performances. In the last decade, a new architecture has been brought into play to realize the frequency synthesis: the Delay Locked Loop (DLL) [4]. In this architecture, the VCO is replaced by a Voltage Controlled Delay Line (VCDL).…”

Section: Introductionmentioning

confidence: 99%

Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO

Majek

Deval

Lapuyade

et al. 2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

View full text Add to dashboard Cite

This paper presents the design and measurement results of a novel VCDL (Voltage Controlled Delay Line). Based on the multiphase ring oscillator technique, it offers two outputs in phase quadrature. These last ones allow the Factorial DLL (F-DLL) to be zero-IF compliant and so a good candidate for multi-standard LO. The proposed circuit has been fabricated using 130 nm CMOS SOI technology from STMicroelectronics. Measurements confirm the low quadrature phase error of the topology and its ability to synthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications.

show abstract

A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer

Cited by 13 publications

References 10 publications

The P/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation

The P/DLL frequency synthesizer architecture: A native trade-off between stability and wideband frequency generation

A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture

Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO

Contact Info

Product

Resources

About