A VLSI Architecture for Variable Block Size Video Motion Estimation

Abstract

Abstract-With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.Index Terms-Advanced video coding (AVC), sum of absolute difference (SAD), variable block size motion estimation (VBSME), very large-scale integration (VLSI) architecture.

Scalable and low cost design approach for variable block size motion estimation (VBSME)

“…Each PE shares data with its neighbors and more parallelism is obtained with fixed memory bandwidth. For lowpower portable devices, 1-dimensional (1D) systolic array implementations of VBSME have been proposed in the past [6,7,12]; 2D arrays have also been proposed for high-end application domains, such as HDTV [1,3], where the power budget is less of a concern; this paper focuses on the former.…”

“…One of the first 1-D VBSME architectures for H.264/AVC was presented by Yap and McCanny [12], and later improved upon by Song et al [7]. Both of these architectures reuse the results of smaller sub-block computations with an irregular workflow inside each PE.…”

A novel fast inter mode decision algorithm based on statistic and adaptive adjustment for H.264/AVC

“…The RDO plays the role of balancing the mode selection in order to get the most suitable encoding performance. However, the RDO enabled MD can choose the best mode only after all 41 possible ME results [9] for one macroblock have been obtained. If the system can prejudge which mode(s) could be abandoned during the early stage of encoding process at the minimum cost in terms of PSNR's degradation and increase of bitrate, the significant encoding time could be reduced drastically.…”

Αλγόριθμοι και υλοποίηση για πρόβλεψη Macroblock στο πρότυπο κωδικοποίησης video H.264

“…The process of finding the best predicted frame is known as standards. There are many methods to support VBSME in hardware but the one used by most of the presented architectures, as for example in [74], [75], [76], [77], [78] and [79], is that of reusing the SADs of the smallest blocks, which are the blocks partitioned with the smallest block size , to derive the SADs of larger blocks. Nevertheless, the proposed architecture, because of the dependency of data occurring in each mode, cannot follow the same logic.…”

“…An other important aspect of the efficiency of an architecture for VBSME is the video format which can be supported by each implementation. C. -M. Ou [75] As it is clear from Table 36 Yap et al [76] presents two normalized units to determine the performance of an architecture for motion estimation. The first is the normalized power consumption, which is defined in terms of the power dissipation per macroblock (MB) per frame per second (fps).…”