A VLSI architecture for a single-chip 5-Mbaud QAM receiver

Joshi, R.B.; Daneshrad, Babak; Samueli, H.

doi:10.1109/glocom.1992.276596

Cited by 9 publications

(1 citation statement)

References 7 publications

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“…With the architectural changes also comes the possibility of integrating the entire receiver on a single IC [34]. The notion of a single chip containing all the necessary receiver functions is quite appealing and is one of the driving forces behind this work.…”

Section: Proposed Modulation Formats For Adslmentioning

confidence: 99%

A 1.6 Mbps digital-QAM system for DSL transmission

Daneshrad¹,

Samueli²

1995

IEEE J. Select. Areas Commun.

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An all digital QAM system is studied here for high-speed data transmission on digital subscriber loops. All elements of the system have been fully investigated and their effects on the overall system performance documented. In particular the following issues have been explicitly addressed: utility of an adaptive error-prediction (noise-prediction) filter; equalizer size and convergence; blind equalization; choice of constellation size and center frequency; combined timing/ carrier recovery, and finally the oversampling requirements of an NCO for potential use in the timing and carrier recovery loop. The paper relies on simulation results to investigate and quantify the overall interactions of the various blocks. Throughout the paper emphasis has been placed on reducing the complexity of the system for implementation on an integrated circuit (IC). It is expected that the information provided here will serve as a good starting point for an IC designer to start the implementation of a transceiver ASIC. .

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Section: Proposed Modulation Formats For Adslmentioning

confidence: 99%