A VLIW architecture stream cryptographic processor for information security

Liu, Nan; Yang, Xuan; Zeng, Xiaoyang; Li, Wei; Du, Yiran; Dai, Zibin; Chen, Lin

doi:10.23919/jcc.2019.06.015

Cited by 2 publications

(6 citation statements)

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“…The stream data is transmitted in IoT device via compression using delta encoding as shown in Figure 7. For the encryption, stream cipher is used as stream cipher has fast processing speed in case of limited computing resources as in IoT 25 . In Figure 8, an example is demonstrating the data transmission mechanism in IoT border router, where the dataset with the data elements, that is, 23, 24, 23, and 25 (in decimal) is compressed and encrypted with key streams 010101, 011, 010 and 110.…”

Section: The Proposed Streamed Data Handling Systemmentioning

confidence: 99%

“…This way it minimizes energy consumption during the computation and saves the battery life of the IoT devices. Existing research ignored prior information of the compression percentage, however, the proposed approach has taken into account how much compression required for any input dataset. This makes it a user‐centered approach. The proposed model uses stream cipher 25,26 for the encryption and decryption in order to ensure the security during the data transmission from client to server side or vice‐versa. Stream cipher is the faster and more secure technique for light‐weighted IoT devices as it uses simple XOR operation, and it is also reliable for data transmission which is continuous in nature.…”

Section: Introductionmentioning

confidence: 99%

“…Stream cipher encryption : A stream cipher 25 is basically a symmetric key cipher. The digits of plain text are combined with the pseudo random cipher digit stream.…”

Section: Introductionmentioning

confidence: 99%

“…This makes it a user-centered approach. • The proposed model uses stream cipher 25,26 for the encryption and decryption in order to ensure the security during the data transmission from client to server side or vice-versa. Stream cipher is the faster and more secure technique for light-weighted IoT devices as it uses simple XOR operation, and it is also reliable for data transmission which is continuous in nature.…”

mentioning

confidence: 99%

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IoT streamed data handling model using delta encoding

Jindal

Kumar

Patidar

2022

Int J Communication

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Summary Internet of Thing (IoT) is a trending internet connectivity extension to connect physical devices on the heterogeneous networks to meet application requirements on various grounds, that is, health, agriculture, industry, and so forth. The amount of streamed data is generated by the IoT devices and processed via IoT device itself or external resources such as Cloud/Fog by considering real‐time constraints. The problem arises in real‐time data transmission when a huge amount of stream data is generated from IoT devices, and it travels through the network and needs to be processed on low‐speed IoT infrastructure. Considering this scenario, there is an extremely requirement for designing a model relying on real‐time stream data handling for speedy transmission considering IoT device real‐time communication constraint. On the other hand, IoT devices are also very sensitive towards energy consumption during the streamed data transmission, and low battery devices become a barrier in data handling in real‐time. To overcome these limitations, a model is proposed to compress and encrypt the data stream during the IoT network transmission. In this model, delta encoding facilitates the compression in form of deltas. To ensure security requirements, a light weighted stream cipher encryption technique is proposed. For the experimentation, a test‐bed setup is prepared to utilize Raspberry Pi (IoT device), CPU, and collectors to collect data stream. The proposed approach is compared with the baseline model, that is, LDPC encoding on temperature sensor datasets. As an outcome, the data are compressed up to 37.59%, and the average transmission time and the average power consumption are reduced by 72.57% and 68.86%, respectively.

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Section: The Proposed Streamed Data Handling Systemmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Stream cipher encryption : A stream cipher 25 is basically a symmetric key cipher. The digits of plain text are combined with the pseudo random cipher digit stream.…”

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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IoT streamed data handling model using delta encoding

Jindal

Kumar

Patidar

2022

Int J Communication

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“…In academia, several studies have been conducted on VLIW architecture implementation on application-specific integrated circuit (ASIC) and FPGA technology. An ASICbased four-slot VLIW for multiple stream cipher operations is fabricated on a 180 nm technology to achieve an operating frequency of 200 MHz [5]. It achieves a good tradeoff between high performance and flexibility for multiple basic stream cipher operations.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

2020

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This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction flows, each of which performs fixed operational functions to create a 256-bit long instruction format. However, one obstacle of studying new ISAs, similar to RISC-V, to design VLIW microprocessors is the lack of dedicated compilers. Developing an architecture-specific compiler is really challenging. An instruction scheduler is integrated to dynamically schedule independent instructions into the VLIW instruction format. This scheduler is used to overcome the lack of a dedicated RISC-V VLIW compiler and leverage the available RISC-V GNU toolchain. Unlike conventional VLIWs, our proposed architecture is organized into six main stages, namely, fetch, instruction scheduler, decode, execute, data memory, and writeback. The complete design is verified, synthesized, and implemented on a Xilinx Virtex-6 (xc6vlx240t-1-ff1156). Maximum synthesis frequency reaches 83.739 MHz. The proposed RISC-V-based VLIW architecture obtains an average instructions per cycle value that outperforms that of existing open-source RISC-V cores. INDEX TERMS very long instruction word (VLIW), RISC-V, microprocessor, dynamic scheduling, fieldprogrammable gate arrays (FPGA)

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A VLIW architecture stream cryptographic processor for information security

Cited by 2 publications

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IoT streamed data handling model using delta encoding

IoT streamed data handling model using delta encoding

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

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