A VLIW architecture for a trace scheduling compiler

Recent trends in microprocessor design heavily rely on large register files with large I/O bandwidths for sustaining performance; a possible solution to relieve this bottleneck is the adoption of multiple register files.In this paper we show how the problem of assigning variables to multiple register banks can be reduced to that of a hypergraph coloring and, also, propose a tech nique to perform this coloring; this technique is applied to the problem of variable partitioning for rnultipltregister-file VLIW architectures.

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“…Consider the read hyperedge containing nodes (1,5,6); it represents the simultaneous access to VRs {R1,R5,R6} read in instruction i2.…”

Section: Register File Assignmentmentioning

confidence: 99%

“…More aggressive designs can make use of multiple banks, both for integer and FP registers, as in the Multiflow Trace architecture [6].…”

Section: Introductionmentioning

confidence: 99%

An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures

Chen

Fuchs

Hwu

1994

1994 International Conference on Parallel Processing Vol. 1

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“…LE1 CONFIGURABILITY LE1 has been architected to be highly parameterizable in both the programmer model (architectural parameterization) as well as its internal organization (microarchitecture customization). The base ISA is an amalgam of the partiallypredicated Multiflow TRACE architecture [11], fullypredicated EPIC architectures [12], augmented with substantial SIMD support [13]. This model (ISA, state) can be extended with additional registers and single/multi-input, multi-output custom extensions.…”

Section: Introductionmentioning

confidence: 99%

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

Stevens

Chouliaras

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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We discuss LE1, a parameterized VLIW Chip Multiprocessor (CMP) adhering to the shared memory programmers model. LE1's novelty lies in its ability to perform dynamic thread-spawning through hardware support for PThread-like primitives in addition to its substantial architectural and microarchitectural parameterization. Dynamic (hardware) thread creation is very fast and removes the need for an executive/OS, presenting to the application programmer a 'bare-metal' multiprocessor, capable of exploiting all forms of parallelism. The core LE1 CPU is a configurable, 8-stage pipeline VLIW engine with a proprietary Instruction Set Architecture (ISA) supporting both partial and full predication and pipelined, multi-input, multi-output (MIMO) instruction extensions. The LE1 CMP is parameterizable as to the number of processors, their issue capability, internal microarchitectural features, functional unit mix and latency and the local memory system architecture.Preliminary results indicate near-linear performance improvement when executing a threaded version of the Mandelbrot calculation on 2-way and 4-way processor configurations with a 256 KB, 4-way banked tightly-coupled memory system. Similar trends are seen when executing a threaded matrix multiplication benchmark. We present these findings along with VLSI implementations of 4-way, dual-issue and 3-way, quad issue multiprocessor configurations.

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“…The coimmunication between clusters happens across a set of global connections, and is explicitly scheduled by the compiler. The Multiflow Trace [5] follows exactly this structure. The reason for clusters, which are not independent, but rather share a single long instruction, is to avoid register banks with too many ports.…”

Section: Clusters and Architectural Parametersmentioning

confidence: 85%

Custom-fit processors: letting applications define architectures

Fisher¹,

Faraboschi²,

Desoli³

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29

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In this paper we report on a system which automatically designs realistic VLIW architectures highly optimized for one given application (the input for this system), while running all other code correctly. The system uses a productquality compiler that generates very aggressive VLJW code. We retarget the compiler until we have found a VLJW architecture idealized for the application on the basis of performance, a cost function and a hardware budget.We show that we can automatically select architectures that achieve large speedups on color and image processing codes. Specialization is shown to be very valuable: The differences between architectural choices, even among reasonable-seeming architectures having similar costs, can be very great, often a factor of 5 (andsometimes much more). We show also that specialization is also very dangerous. A reasonable choice of architecture to fit one algorithm can be a very poor choice for anothel; even in the same domain.There is sometimes an architecture, near in cost and performance to the best, that does much better on a second algorithm.

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A VLIW architecture for a trace scheduling compiler

Cited by 204 publications

References 17 publications

An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures

An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

Custom-fit processors: letting applications define architectures

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