A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC

Toyokura, M.; Saishi, M.; Kurohmaru, S.; Yamauchi, Kohei; Imanishi, H.; Ougi, T.; Watabe, Akihiko; Matsumoto, Y.; Morishige, T.; Kodama, Hisashi; Miyagoshi, E.; Okamoto, K.; Gion, M.; Minemaru, T.; Ohtani, Akira; Araki, Takashi; Aono, K.; Takeno, H.; Akiyama, Tetsuya; Wilson, Beth Anne

doi:10.1109/4.340420

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Features Of the Mpeg-2 Algorithm1

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Cited by 32 publications

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“…Although some units can operate on a block basis (e.g. DQ and IQ), the MB is the basic unit of processing for the whole set of units [12]. So, we have used this feature to design an architecture with a MB-Level-Pipeline basis, called MViP (MPEG-2 Video Processor).…”

Section: Features Of the Mpeg-2 Algorithmmentioning

confidence: 99%

A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

1996

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Section: Features Of the Mpeg-2 Algorithmmentioning

confidence: 99%

A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

1996

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“…Most designs which have already been published on motion estimation in related MPEG video coders [5,13,18] are based on a systolic array type approach because of the relatively large frame sizes involved, leading to a large computational requirement on the DCT. However, in the video conferencing case, this is not needed.…”

Section: Related Workmentioning

confidence: 99%