A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback

Abstract

The design of an Evolvable Machine VHDL Core is presented, representing a discrete-time processing structure capable of supporting control system applications. This VHDL Core is implemented in an FPGA and is interfaced with an evolutionary algorithm implemented in firmware on a Digital Signal Processor (DSP) to create an evolvable system platform. The salient features of this architecture are presented. The capability to implement IIR filter structures is presented along with the results of the intrinsic evolution of a Jilter. The robustness of the evolved filter design is tested and its unique characteristics are described.

Evolvable Hardware

“…In particular, structures of multiplierless filters were sought by many authors (Wade et al 1994;Hounsell et al 2004;Erba et al 2001;Gwaltney and Dutton 2005). Regardless of filter representation, the fitness function is usually constructed in the frequency domain.…”

Evolutionary functional recovery in virtual reconfigurable circuits

“…The following list shows examples of evolvable systems which were implemented using the idea of the VRC on an FPGA: -evolvable image filter for the evolution of 3x3 image operators (EA is implemented either in PC [Zhang et al 2004] or on the same FPGA as a special circuit [Martinek and Sekanina 2005] or in an on-chip PowerPC processor [Vasicek and Sekanina 2007]); -evolvable sorting network for up to 28 inputs (EA is implemented on the same FPGA) [Korenek and Sekanina 2005]; -evolvable combinational circuits (EA is implemented on the same FPGA as a special circuit [Sekanina and Friedl 2004] or in the PowerPC processor on the same FPGA [Glette and Torresen 2005]); -intrinsic evolution of polymorphic combinational modules (EA is implemented on the same FPGA) ]; -evolvable IIR filter (EA is implemented on a DSP) [Gwaltney and Dutton 2005]; -packet classifiers (EA is implemented as a special circuit on the same FPGA) [Salomon et al 2006]. …”

“…Because a designer can construct the VRC so that it exactly fits the needs of a given evolvable hardware-based application, a perfect reconfigurable device can be obtained for a given problem. Examples include VRCs for the evolution of logic circuits [Sekanina and Friedl 2004], image filters [Martinek and Sekanina 2005], IIR filters [Gwaltney and Dutton 2005], sorting networks [Korenek and Sekanina 2005], or packet classifiers [Salomon et al 2006]. As the evolutionary algorithm can be implemented on the same FPGA (as an application-specific circuit or in a processor) in these applications, a fast configuration interface can be established connecting the configuration memory of VRC with chromosomes of EA.…”

Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling

“…This approach mainly involves External reconfiguration [12] Tone discriminator [13] Oscillators [14] Sorting networks [15] Arithmetic circuits [16] Image filters [17] IIR filters [18] FT a arith. circuits…”