DOI: 10.1007/978-3-540-85053-3_20
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A Very Compact Hardware Implementation of the MISTY1 Block Cipher

Abstract: Abstract. This paper proposes compact hardware (H/W) implementation for the MISTY1 block cipher, which is an ISO/IEC18033 standard encryption algorithm. In designing the compact H/W, we focused on optimizing the implementation of FO/FI functions, which are the main components of MISTY1. For this optimization, we propose two new methods; reducing temporary registers for the FO function, and shortening the critical path for the FI function. According to our logic synthesis on a 0.18-µm CMOS standard cell library… Show more

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Cited by 8 publications
(4 citation statements)
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References 5 publications
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“…MISTY-1 is later replaced by it successors: MISTY-2 and KASUMI, which is also covered in this article. The work by Yamamoto et al (2008) has presented a small hardware for MISTY-1 64-bit cipher using the Fujitsu 0.18-mm CMOS standard cell library. The simulated result shows a gate size of 3.95 Kgates, focusing on the optimization of the FO/FI functions.…”
Section: Misty-1mentioning
confidence: 99%
“…MISTY-1 is later replaced by it successors: MISTY-2 and KASUMI, which is also covered in this article. The work by Yamamoto et al (2008) has presented a small hardware for MISTY-1 64-bit cipher using the Fujitsu 0.18-mm CMOS standard cell library. The simulated result shows a gate size of 3.95 Kgates, focusing on the optimization of the FO/FI functions.…”
Section: Misty-1mentioning
confidence: 99%
“…A detailed study has been carried out on the existing hardware designs of MISTY1, KASUMI, AES, SHA-1, CAMELLIA and SAFER [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The review covered the comparison of performance parameters i.e.…”
Section: Introductionmentioning
confidence: 99%
“…In comparison to high throughput encryption cores, compact designs make use of the logic optimization techniques for transformation functions and s-boxes using combinational logic [5][6][7][8][9][10], [12][13][14][15][16][17][18], [21], [22]. Besides, re-utilization methodologies have also been implemented exploiting the rolling-feature of the architecture.…”
Section: Introductionmentioning
confidence: 99%
“…In [4], Yamamoto et al proposed the method of reducing temporary registers for the MISTY1 FO function from 32 bits to 16 bits (YYI-08), and implemented a very compact H/W of MISTY1 [5]. KASUMI has a similarly structured MISTY1 FO function.…”
Section: Introductionmentioning
confidence: 99%