A versatile framework for FPGA field updates: an application of partial self-reconfiguration

Fong, Ryan Joseph Lim; Harper, Scott; Athanas, Peter

doi:10.1109/iwrsp.2003.1207038

Cited by 36 publications

(22 citation statements)

References 5 publications

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“…However, the cryptographic key on which its security depends is obfuscated in a non-encrypted bitstream stored in the local NVM. Fong et al [9] propose a security controller based on the Blowfish block cipher for encryption and CRC for data correctness. Attached to a "Media Interface", the FPGA is able to receive updates that are programmed into the configuration logic through the internal configuration port.…”

Section: Related Workmentioning

confidence: 99%

A Protocol for Secure Remote Updates of FPGA Configurations

Drimer

Kühn

2009

Lecture Notes in Computer Science

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Abstract. We present a security protocol for the remote update of volatile FPGA configurations stored in non-volatile memory. Our approach can be implemented on existing FPGAs, as it sits entirely in user logic. Our protocol provides for remote attestation of the running configuration and the status of the upload process. It authenticates the uploading party both before initiating the upload and before completing it, to both limit a denial-of-service attack and protect the integrity of the bitstream. Encryption protects bitstream confidentiality in transit; we either decrypt it before non-volatile storage, or pass on ciphertext if the configuration logic can decrypt it. We discuss how tamper-proofing the connection between the FPGA and the non-volatile memory, as well as space for multiple bitstreams in the latter, can improve resilience against downgrading and denial-of-service attacks.

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Section: Related Workmentioning

confidence: 99%

A Protocol for Secure Remote Updates of FPGA Configurations

Drimer

Kühn

2009

Lecture Notes in Computer Science

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“…The active or dynamic reconfiguration allows the modification of a part of the FPGA while the remaining part of the device is active [113]. Thanks to the internal configuration access port (ICAP) the reconfiguration management can be implemented in the FPGA so that the final system is self-reconfigurable [114], [115].…”

Section: Dynamic Partial Reconfiguration (Dpr)mentioning

confidence: 99%

Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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A AbstractRecently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

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“…When both these features are available, the FPGA is called partially dynamically reconfigurable. Although there are several techniques to exploit partial reconfiguration (e. g. [6,17,18]), there are only a few aprroaches for frameworks and tools (e. g. [8,10,[17][18][19]) to design dynamically reconfigurable System on Programmable Chip,SoPC (e. g. [20][21][22]). Examples of such frameworks are the operating systems for reconfigurable embedded platforms which have been analyzed in [23].…”

Section: Overview On Reconfigurable De-signmentioning

confidence: 99%

Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign

Santambrogio

Sciuto

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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Many emerging products in communication, computing and consumer electronics demand that their functionality remains flexible also after the system has been manufactured and that is why the reconfiguration is starting to be considered into the design flow as a new relevant degree of freedom, in which the designer can have the system autonomously modify its functionalities according to the application's changing needs. Therefore, reconfigurable devices, such as FPGAs, introduce yet another degree of freedom in the design workflow: the designer can have the system autonomously modify the functionality carried out by the IP core according to the application's changing needs while it runs. Research in this field is, indeed, being driven towards a more thorough exploitation of the reconfiguration capabilities of such devices, so as to take advantage of them not only at compile-time, i.e. at the time when the system is first deployed, but also at run-time, which allows the reconfigurable device to be reprogrammed without the rest of the system having to stop running. This paper presents emerging methodologies to design reconfigurable applications, providing, as an example the workflow defined at the Politecnico di Milano.

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A versatile framework for FPGA field updates: an application of partial self-reconfiguration

Cited by 36 publications

References 5 publications

A Protocol for Secure Remote Updates of FPGA Configurations

A Protocol for Secure Remote Updates of FPGA Configurations

Efficient reconfigurable architectures for 3D medical image compression

Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign

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