A Verilog piecewise-linear analog behavior model for mixed-signal validation

Abstract

Full chip mixed-signal validation requires simulating the entire design through a large number of test vectors, which makes fast, event-based Verilog models of analog circuits essential. We describe an extensible approach to creating these models that maps continuous signals into piecewise linear waveforms by creating analog events which contain a value and slope. By breaking analog circuits into sub-blocks with mostly unidirectional ports, we avoid explicit time integration, thus fitting well into an event-driven digital framework. The result is Verilog analog functional models that are pin-accurate, fast to simulate and capture the key dynamics in analog circuits. A 2.5V-1.8V buck converter and 1GHz PLL models are demonstrated. I. INTRODUCTIONMixed-signal systems in which digital and analog circuits communicate across a tight interface are commonplace today. This tight coupling compounded with the large complexity of the system, and the large number of test vectors that need to be run at the system level requires efficient system-level simulation models. The only practical means of performing this validation is through efficient HDL simulator [8]. Thus it is essential to have analog functional models that would fit seamlessly into the digital validation framework.Given the importance of full system simulation, there has been considerable work in this area. Verilog-AMS based method is one example [2]. These behavioral models use differential equations and time integration, and hence require solvers similar to those found in circuit simulators. Matlab/Simulink [6] is another common route. While these models are faster than the Verilog-AMS models, they are run in Matlab's event-driven simulator and have little resemblance to the physical circuit thereby limiting their value in validation effort. Analog behavioral modeling has also been attempted in digital Verilog and these models are typically constant timestep based. In [8], FIR filters and adjustable circuit parameters such as multiple biases were implemented. In [5], the constant time-step approach is supplemented with additional data such as the actual crossing time of a clock transition. There is also a large body of related research in macromodeling ([1],[4],[7]), which attempts to create extremely accurate models to replace SPICE simulation entirely.

Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface

“…It takes an excessively long time to perform the mixed-mode simulation of the circuit, which contains both Verilog and SPICE netlist, For example, it takes around two days to finish the mixed-mode simulation of a USB 2.0 highspeed interface for the time interval of 3us with a recent desktop PC. For the simulation of chip-to-chip interface, the MATLAB model [2] or the Verilog-AMS model [3,4] were used. In the MATLAB model, the simulation time is much shorter than the mixed-mode simulator such as SPECTRE, since both transmission line and chip are modeled in MATLAB.…”