Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface

Abstract

Abstract-A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

EMI Issues in Pseudo-Differential Signaling for SDRAM Interface

“…In the differential signaling, a small-area current-loop is generated ( Fig. 1(b)) because the current loop is formed along the pair of the microstrip differential transmission line without going through the PCB ground plane [4]. Because EMI intensity is proportional to the current-loop area, the differential signaling generates a much less EMI.…”