A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing

Li, Kai; Zhou, Junzhuo; Li, Boyu; Yang, Shuxing; Huang, Sixiao; Luo, Shaobo; Mao, Wei; Yu, Hao

doi:10.1109/aicas54282.2022.9869969

Cited by 5 publications

(1 citation statement)

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“…3(b). The alignment may involve either the output of the multiplier, or the incoming partial addition result [29], [30]. This approach is a more natural fit to the delay profiles observed with the new FP formats.…”

Section: Systolic Arrays Using Fp Arithmeticmentioning

confidence: 99%

Templatized Fused Vector Floating-Point Dot Product for High-Level Synthesis

Filippas

Nicopoulos

Dimitrakopoulos

2022

JLPEA

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Machine-learning accelerators rely on floating-point matrix and vector multiplication kernels. To reduce their cost, customized many-term fused architectures are preferred, which improve the latency, power, and area of the designs. In this work, we design a parameterized fused many-term floating-point dot product architecture that is ready for high-level synthesis. In this way, we can exploit the efficiency offered by a well-structured fused dot-product architecture and the freedom offered by high-level synthesis in tuning the design’s pipeline to the selected floating-point format and architectural constraints. When compared with optimized dot-product units implemented directly in RTL, the proposed design offers lower-latency implementations under the same clock frequency with marginal area savings. This result holds for a variety of floating-point formats, including standard and reduced-precision representations.

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Section: Systolic Arrays Using Fp Arithmeticmentioning

confidence: 99%