A unified methodology for pre-silicon verification and post-silicon validation

Adir, Allon; Copty, Shady; Landa, Shimon; Nahir, Amir; Shurek, Gil; Ziv, Avi; Meissner, Charles; Schumann, John

doi:10.1109/date.2011.5763252

Cited by 48 publications

(31 citation statements)

References 7 publications

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“…Constrained-random stimuli combined with assertion checking are the dominant tools used in practice during pre-silicon verification. Using a similar approach for post-silicon validation has been successfully deployed for microprocessors [1]. Nonetheless, for generic circuits, though there are known techniques to implement assertions into hardware [2], it is less obvious how one can port constrained-random stimuli in a systematic manner.…”

Section: Motivationmentioning

confidence: 98%

On-chip stimuli generation for post-silicon validation

Nicolici

2012

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)

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In contrast to pre-silicon verification environments, insystem validation is not strongly constrained by the number of stimuli that can be applied; rather, the quality of the patterns, as well as the observation of the events of interest are the real concern. This paper motivates the need for developing structured methods for porting the controllability aspects of pre-silicon verification into post-silicon validation environments. Use cases and challenges for such methods are outlined.

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Section: Motivationmentioning

confidence: 98%

On-chip stimuli generation for post-silicon validation

Nicolici

2012

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)

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“…One approach to post-silicon test generation is Automatic Test Pattern Generation (ATPG) [22], [23], which targets exposing electrical and manufacturing defects rather than functional errors. There has also been efforts on reusing pre-silicon validation tests in post-silicon validation [24], [25]. Our approach shares the same goal of bridging the gap between pre-silicon and post-silicon validation, while fully leveraging the white box nature of virtual prototypes to efficiently generate high-quality functional tests.…”

Section: Related Workmentioning

confidence: 99%

Automatic concolic test generation with virtual prototypes for post-silicon validation

Cong

Xie

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Post-silicon validation is a crucial stage in the system development cycle. To accelerate post-silicon validation, high-quality tests should be ready before the first silicon prototype becomes available. In this paper, we present a concolic testing approach to generation of post-silicon tests with virtual prototypes. We identify device states under test from concrete executions of a virtual prototype based on the concept of device transaction, symbolically execute the virtual prototype from these device states to generate tests, and issue the generated tests concretely to the silicon device. We have applied this approach to virtual prototypes of three network adapters to generate their tests. The generated test cases have been issued to both virtual prototypes and silicon devices. We observed significant coverage improvement with generated test cases. Furthermore, we detected 20 inconsistencies between virtual prototypes and silicon devices, each of which reveals a virtual prototype or silicon device defect.

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“…However, while there has been some initial work in this area [3]- [5], most of this work has been focused on very specific ''one-off'' examples, and there is not yet a common set of best practices, an automated tool flow, or a set of targeted electronic design automation (EDA) tools in this area. Hence, for most FPGA, ASIC, and SoC developments, preimplementation verification and post-implementation validation remain quite disconnected.…”

mentioning

confidence: 99%

“…With each new generation of a device, testing must cover more functionality, typically with similar resources in the same timeframe [1], [2]. Designers make extensive use of both verification (testing the design before the chip is built) and validation (testing the fabricated chip) [3]. Verification and validation are complementary; neither can lay claim to a complete solution to the problem of ensuring device correctness.…”

mentioning

confidence: 99%

Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics

2013

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h CURRENT STATE-OF-THE-ART INTEGRATED circuits can be several billions of transistors in size, and ensuring that they function correctly is becoming increasingly difficult. Applying effective testing is crucial to this goal, yet pre-implementation verification is limited by the speed of software simulation, while post-implementation validation is hampered by the lack of on-chip visibility. In this paper, we present a method to bridge the pre-and post-implementation worlds by using shared coverage metrics for evaluating test effectiveness. We show that coverage measurement can be enabled on field-programmable gate array (FPGA) designs, and FPGA-based prototypes that act as a proxy for application-specific integrated circuits (ASICs) and SoCs, using currently available secondgeneration trace instruments. We then show how emerging research on thirdgeneration instruments can be used to acquire even more complete coverage measurements.FPGAs, ASICs, and SoCs have become fundamental to all aspects of modern life, from smartphones and bank machines, to aircraft and automobiles. As the performance and complexity of these devices increase, it is increasingly challenging to ensure that they work correctly. With each new generation of a device, testing must cover more functionality, typically with similar resources in the same timeframe [1], [2]. Designers make extensive use of both verification (testing the design before the chip is built) and validation (testing the fabricated chip) [3]. Verification and validation are complementary; neither can lay claim to a complete solution to the problem of ensuring device correctness. Verification is severely limited by slow operation of software-based models, while validation is limited by the lack of control and observability once devices are implemented in silicon.Given that they face many of the same challenges, share the same end goal (correct device operation), and rely on each other for overall success, it seems intuitive that verification and validation could work together to mutual benefit, by agreeing on shared metrics of effectiveness (commonly called Editors' notes: This paper discusses the current state of the art in measuring validation coverage through embedded instrumentation in FPGAs and presents new instrumentation that allows any cover point to be measured.

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A unified methodology for pre-silicon verification and post-silicon validation

Cited by 48 publications

References 7 publications

On-chip stimuli generation for post-silicon validation

On-chip stimuli generation for post-silicon validation

Automatic concolic test generation with virtual prototypes for post-silicon validation

Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics

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