A unified approach to topology generation and optimal sizing of floorplans

Dasgupta, Parthasarathi; Sur-Kolay, Susmita; Bhattacharya, Bhaswar B.

doi:10.1109/43.681262

Cited by 8 publications

(16 citation statements)

References 16 publications

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“…Based on these conditions, we adapt the unified floorplan optimization method of Dasgupta et al [1995a;1995b;1998] to generate rectangular floorplans with smaller memory and CPU time requirements. For an input graph, we first detect all the complex 4-cycles and if these are maximal, that is, not contained in any other complex 4-cycle, an area-optimal slicible floorplan is produced.…”

Section: Resultsmentioning

confidence: 99%

“…The subgraph contained within a maximal complex 4-cycle is replaced by a super-vertex. The method suggested in Dasgupta et al [1995b;1998] is then recursively applied to the reduced graph, and the expanded versions of the super-vertices. At any level of the recursion, our tighter conditions are once again used to decide whether the corresponding subfloorplan to be generated is slicible.…”

Section: Resultsmentioning

confidence: 99%

“…The unified floorplan optimization method AO F P * based on AND-OR graphs as described in Dasgupta et al [1995b;1998] is then applied toG with the addition of checking of condition (1) in Theorem 1 for the subgraphs G l and G r . The same graph reduction procedure as explained above is applied recursively to each of these subgraphs.…”

Section: Unified Topology Generation and Optimal Sizingmentioning

confidence: 99%

“…In many cases, a good estimate for the areas of the building blocks are available at this stage, although their aspect ratios may vary over a wide range. Area-optimal floorplan generation based on graph dualization appears in Yeap and Sarrafzadeh [1993] and Dasgupta et al [1995;1998]; these algorithms for the topology generation and area optimization are applicable to both slicible and nonslicible floorplans.…”

Section: Introductionmentioning

confidence: 99%

“…Slicing topologies can facilitate the subsequent routing phase in channel routing as well as area routing approaches [Sherwani 1993]. While Stockmeyer's polynomial time sizing algorithm for slicible floorplans may violate some of the module adjacencies, the number of such violations happen to be fairly small [Dasgupta et al 1998] if the topology generation is performed judiciously. Our theoretical results in this paper characterize a larger class of slicible graphs.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Slicible rectangular graphs and their optimal floorplans

Dasgupta

Sur-Kolay

2001

ACM Trans. Des. Autom. Electron. Syst.

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Rectangular dualization method of floorplanning usually involves topology generation followed by sizing. Slicible topologies are often preferred for their simplicity and efficiency. While slicible topologies can be obtained efficiently, existing linear-time algorithms for topology generation from a given rectangular graph does not guarantee slicible topologies even if one exists. Moreover, the class of rectangular graphs, known as inherently nonslicible graphs, do not have any slicible topologies. In this article, new tighter sufficiency conditions for slicibility of rectangular graphs are postulated and utilized in the generation of area-optimal floorplans. These graph-theoretic conditions not only capture a larger class of slicible rectangular graphs but also help in reducing the total effort for topology generation, and in solving problems of larger size.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Unified Topology Generation and Optimal Sizingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Slicible rectangular graphs and their optimal floorplans

Dasgupta

Sur-Kolay

2001

ACM Trans. Des. Autom. Electron. Syst.

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Enumeration technique in very large‐scale integration fixed‐outline floorplanning

Hoo

Kanesan

Ramiah

2014

IET Circuits, Devices & Systems

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Even though enumeration is a common technique adapted in very large-scale integration (VLSI) floorplanning, its impact in terms of wirelength, whitespace, as well as runtime on the floorplanning has never been investigated comprehensively. In this study, enumerative floorplanner (EFP) is proposed here by using enumeration. The impact of the maximum enumeration order on VLSI floorplan layout is investigated and the tradeoff relationship with the wirelength, area and runtime is analysed as well. In EFP, dynamic programming enumerative clustering (DEC) technique is employed to reduce the worst-case time complexity and runtime. DEC also introduces the same number of possible permutations of modules while reducing the redundancy created in enumerative clustering (EC) without the usage of dynamic programming. A straightforward cost function is adapted to assist DEC to select the best cluster permutation, and a rigorous local refinement is proposed to compensate the EC's impact on the floorplan wirelength. Experimental results show that EFP is a high performance floorplanner when compared to existing methods in terms of robustness, scalability and stability.

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