A Two-Speed, Radix-4, Serial–Parallel Multiplier

Moss, D.; Boland, David; Leong, Philip H. W.

doi:10.1109/tvlsi.2018.2883645

Cited by 44 publications

(5 citation statements)

References 15 publications

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“…To address these constraints, this study devised a stress classification technique that utilizes the multi-dimensional feature fusion of LSTM and Xception. Further, to address the problem of morphological damages in ECG caused by motion artifacts, which can reduce the effectiveness of the proposed technique, outlier signals were eliminated from the ECG data [19]. A power-efficient FFT processor is designed for embedded DSP systems, focusing on variable-length processing.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of Novel Sense Amplifier for bio- medical Applications

Bikki

2024

Preprint

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This paper presents the realization of a novel sense amplifier for biomedical applications, with a primary focus on its application in cardiac pacemakers. The researchers focus on low-power biomedical devices, achieving this by advanced active devices like the Differential Voltage Current Conveyor (DVCC). In a pacemaker, both sensing and pacing functions are crucial. The sense amplifier consists of an instrumentation amplifier, a bandpass filter, and a comparator, enabling it to recognize the PQRST complex in the cardiac cycle. We introduce a novel model for the sense amplifier, employing a DVCC, and conduct analyses using the TSMC 130 nm technology. The gain of the current-mode instrumentation amplifier (CMIA) is 56.3, and the CMRR is 60.7. Moreover, the proposed design analysis addresses power dissipation, temperature, and noise. Furthermore, experiments performed with the analog IC AD844 have demonstrated the efficiency of the proposed sense amplifier design. Additionally, we analyzed the ECG (electrocardiogram) signal by identifying its patterns. We have used the Fast Fourier transform (FFT) to determine the power spectrum and frequency response of the signal. Studies that looked at signal analysis in the literature used radix-2, SRFFT, and other algorithms. These can save up to 5.066% of power compared to using an FFT ASIC. Hence, we proposed a modified radix-2 approach for the low power spectrum of an ECG cycle. The Radix-2 customized method drastically reduces the number of computations, resulting in a low power consumption of 3.339 mW, and a leakage power of 1.272 mW. Furthermore, it would promote real-time adaptability and increase accuracy in pattern recognition for ECG signals. The results demonstrate that the new sense amplifier model achieves substantial gain and a CMRR, making it more efficient than previous versions.

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Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of Novel Sense Amplifier for bio- medical Applications

Bikki

2024

Preprint

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“…A modified Radix-4 Booth multiplier that only adds non-zero Booth encodings and disregards zero operations 18 . To do the hard multiple 3X operations, use 3X = 2X + X 19 .…”

Section: Related Workmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques—Radix-4 and Radix-8—with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

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“…Radix-4, serial -parallel multiplier is designed by Moss et al (2018) for improving the performance of different applications like filtering, machine learning and neural network-based systems [30]. This multiplier is realized by Intel Cyclone V FPGA for 32-bit and 64-bit operations.…”

Section: Liu Et Al 2016 Designed An Approximate Radix-4 Boothmentioning

confidence: 99%

“…Both ABM and STBMBM [23] are used for finite impulse responnse (FIR) filter. SPM [30] is used for implementing filter as well as meachine learning (ML) algorithms. DABMAU [27] is applied for desigining discrete wavelet transform (DWT) and B2CBBM [29] is suitable for implementing graphical processor units (GPU).…”

Section: Comparative Analysismentioning

confidence: 99%

VLSI Architectures of Booth Multiplication Algorithms – A Review

Hareesh¹,

C²,

Prasad³

2022

IJCDS

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The Booth multiplication scheme plays a major role in designing signed multiplier using multiplier encoder and by decreasing the number of intermediate products. Both radix-4 and radix-8 Booth encoding schemes are widely used due to simple and fast respectively. Multiplier is one of the basic as well as an important part in arithmetic unit of many high-performance operations like digital signal processing (DSP) and digital image processing (DIP) and other high-performance central processing unit (CPU) operation. In the past decade numerous ways of Booth multiplier circuits have been implemented by using different application specific integrated circuit (ASIC) technology like Taiwan semiconductor manufacturing technology (TSMC) 45 nm and 65 nm complementary metal oxide semiconductor (CMOS) process and some of the implementations have been proposed by field programmable gate array (FPGA). This work analyses the very large-scale integration (VLSI) characteristics such as area utilization, power consumption and speed of operation of different types of implementation of Booth multiplication scheme. Based on the exhaustive examination on Booth multiplication scheme, it is noticed that the recent implementation of approximate computing-based and modified two's complementor-based multiplication algorithms outperform other multiplication schemes. Further, the VLSI technology using ST Microelectronics (STM) 28 nm and TSMC 45 nm CMOS processes beat the other implantation schemes by providing less-area and power as well as high-speed of multiplication, respectively.

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A Two-Speed, Radix-4, Serial–Parallel Multiplier

Cited by 44 publications

References 15 publications

Design and Analysis of Novel Sense Amplifier for bio- medical Applications

Design and Analysis of Novel Sense Amplifier for bio- medical Applications

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

VLSI Architectures of Booth Multiplication Algorithms – A Review

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