A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

Fujiwara, Haruhiko; Nii, Koji; Miyakoshi, Junichi; Murachi, Yuichiro; Morita, Yasuhiro; Kawaguchi, Hiroshi; Yoshimoto, Masahiko

doi:10.1145/1165573.1165589

Cited by 12 publications

(3 citation statements)

References 7 publications

(9 reference statements)

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“…Due to the large parasitic capacitance, most low-power encoding focuses on power savings in planar metal wires and 3D through-silicon-via interconnect [5]- [11]. Also, lowpower coding for memories and memory buses has been researched [12], [13].…”

Section: Related Workmentioning

confidence: 99%

Exploiting Neural-Network Statistics for Low-Power DNN Inference

Bamberg,

Najafi,

Garcia-Ortiz

2024

IEEE Open J. Circuits Syst.

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Specialized compute blocks have been developed for efficient DNN execution. However, due to the vast amount of data and parameter movements, the interconnects and on-chip memories form another bottleneck, impairing power and performance. This work addresses this bottleneck by contributing a low-power technique for edge-AI inference engines that combines overhead-free coding with a statistical analysis of the data and parameters of neural networks. Our approach reduces the power consumption of the logic, interconnect, and memory blocks used for data storage and movements by up to 80 % for state-of-the-art benchmarks while providing additional power savings for the compute blocks by up to 39 %. These power improvements are achieved with no loss of accuracy and negligible hardware cost.INDEX TERMS Artificial intelligence, edge-AI inference, low-power coding, low-power digital design, neural networks.

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Section: Related Workmentioning

confidence: 99%

Exploiting Neural-Network Statistics for Low-Power DNN Inference

Bamberg,

Najafi,

Garcia-Ortiz

2024

IEEE Open J. Circuits Syst.

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“…) is used in processing image frame buffers [1,2,3]. Videos have multiple frames that need to be stored.…”

Section: Sram (Static Random Access Memoriesmentioning

confidence: 99%

“…As there is high amount of temporal locality between subsequent video frames, usually the differential between the master frame and adjecent frames is stored on disk. The master frame is stored in a SRAM system that predominently only reads this frame [1,2].SRAM memory system for image and video processing in application specific integrated circuits (ASICs) consume upto 81% of the power as standby/leakage power [4].…”

Section: Sram (Static Random Access Memoriesmentioning

confidence: 99%

Design and Analysis of Low Power SRAM using CMOS Technology

2019

IJITEE

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The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This paper presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The paper also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings..

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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

Noguchi

Iguchi

Fujiwara

et al. 2008

IEICE Transactions on Electronics

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We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.

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A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

Cited by 12 publications

References 7 publications

Exploiting Neural-Network Statistics for Low-Power DNN Inference

Exploiting Neural-Network Statistics for Low-Power DNN Inference

Design and Analysis of Low Power SRAM using CMOS Technology

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

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