A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

Abstract

We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.

Design and Analysis of Low Power SRAM using CMOS Technology

“…As there is high amount of temporal locality between subsequent video frames, usually the differential between the master frame and adjecent frames is stored on disk. The master frame is stored in a SRAM system that predominently only reads this frame [1,2].SRAM memory system for image and video processing in application specific integrated circuits (ASICs) consume upto 81% of the power as standby/leakage power [4].…”

Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential

“…Each macro is 64 kb (128 b × 512 b). The 8T and 10T-S SRAM macros have 16 memory cell blocks (64 b × 64 b), and the divided factor between local RBL and global RBL is eight, which has been optimized by using Elmore delay model 8) . The 10T-D SRAM macro has four memory cell blocks (64 b × 256 b) and the divided factor between local RBL and global RBL is two.…”