A Two-Dimensional Associative Processor

Yantır, Hasan Erdem; Eltawil, Ahmed M.; Kurdahi, Fadi

doi:10.1109/tvlsi.2018.2827262

Cited by 16 publications

(8 citation statements)

References 30 publications

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“…At that point, a truly in-memory implementation of these applications on APs can provide more benefits than GPU-based implementations. Many studies in the literature prove that AP-based implementations of data-intensive applications have superior performance than the traditional correspondences [20,[40][41][42][43], including the applications that has processing flow similar to stencil codes like fast Fourier Transform (FFT) [44]. Therefore, it is obvious that another memory-bound application of the stencil code can get a benefit, which is the main idea of this study.…”

Section: Stencil Codesmentioning

confidence: 97%

Efficient Acceleration of Stencil Applications through In-Memory Computing

2020

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The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of big data and artificial intelligence. This fact forces new constraints in computer architecture design towards more data-centric principles. Therefore, new paradigms such as in-memory and near-memory processors have begun to emerge to counteract the memory bottleneck by bringing memory closer to computation or integrating them. Associative processors are a promising candidate for in-memory computation, which combines the processor and memory in the same location to alleviate the memory bottleneck. One of the applications that need iterative processing of a huge amount of data is stencil codes. Considering this feature, associative processors can provide a paramount advantage for stencil codes. For demonstration, two in-memory associative processor architectures for 2D stencil codes are proposed, implemented by both emerging memristor and traditional SRAM technologies. The proposed architecture achieves a promising efficiency for a variety of stencil applications and thus proves its applicability for scientific stencil computing.

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Section: Stencil Codesmentioning

confidence: 97%

Efficient Acceleration of Stencil Applications through In-Memory Computing

2020

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“…1) Compare: For every pass of the LUT, a masked key takes on the input vector values of this pass (see Table VI for the example of binary AP addition [6]). The masked key is applied to all rows of the array and compared against the stored input data.…”

Section: Ap Operationmentioning

confidence: 99%

“…Considering its promising applications potential, different implementations for the TCAM have been proposed including SRAM-based TCAM [4], [5]. However, they were not widely adopted due to their low density and nonvolatility [6]. Nowadays, emerging devices such as resistive memories have relaxed these constraints, leading to the revival of the TCAM-based AP approach in the research community [7].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Memristive-based TCAM (MTCAM) designs have been proposed to build 1D and 2D in-memory computing architectures based on AP [6], [10]. The AP architecture presented in [6] was designed to perform in-memory compute in the context of the binary full adder. It relies on a look-up table (LUT)based 1-bit addition that employs four compare and write operations applied in parallel to the different rows, resulting in significant runtime savings.…”

Section: Introductionmentioning

confidence: 99%

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In-memory Multi-valued Associative Processor

Hout¹,

Fouda²,

Kanj³

2021

Preprint

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In-memory associative processor architectures are offered as a great candidate to overcome memory-wall bottleneck and to enable vector/parallel arithmetic operations. In this paper, we extend the functionality of the associative processor to multi-valued arithmetic. To allow for in-memory compute implementation of arithmetic or logic functions, we propose a structured methodology enabling the automatic generation of the corresponding look-up tables (LUTs). We propose two approaches to build the LUTs: a first approach that formalizes the intuition behind LUT pass ordering and a more optimized approach that reduces the number of required write cycles. To demonstrate these methodologies, we present a novel ternary associative processor (TAP) architecture that is employed to implement efficient ternary vector in-place addition. A SPICE-MATLAB co-simulator is implemented to test the functionality of the TAP and to evaluate the performance of the proposed AP ternary in-place adder implementations in terms of energy, delay, and area. Results show that compared to the binary AP adder, the ternary AP adder results in a 12.25% and 6.2% reduction in energy and area, respectively. The ternary AP also demonstrates a 52.64% reduction in energy and a delay that is up to 9.5x smaller when compared to a state-of-art ternary carry-lookahead adder.

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