A two-chip 1.5-GBd serial link interface

Walker, Richard; Stout, Cheryl; Wu, Jieh-Tsorng; Lai, B.; Yen, C.-S.; Hornak, T.; Petruno, P.

doi:10.1109/4.173109

Cited by 43 publications

(14 citation statements)

References 3 publications

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“…As in [8], [9] we confine our study to a first-order loop or to a second-order loop satisfying K P K I ; the latter assumption corresponds to an overdamped loop and is usually satisfied in practice [2], [17], [18]. Thus we approximate (3)-(4) by the first-order stochastic difference equation…”

Section: Dbbpll Architecture and Modelmentioning

confidence: 99%

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Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

Tertinek

Gleeson

Feely

2010

IEEE Trans. Circuits Syst. II

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Publication information IEEE Transactions on Circuits and SystemsAbstract-Bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear transfer functions in the analysis. In contrast to a linear PD, the linearized gain of a BPD depends on the rms jitter and the type of jitter (either non-accumulative or accumulative). Previous works considered the case of nonaccumulative reference clock jitter and showed that the BPD gain is inversely proportional to the rms jitter when the latter is small or large. In this brief we consider the case of accumulative DCO jitter and derive an asymptotic closed-form expression for the BPD gain which becomes exact in the limit of small and large jitter. Contrary to the reference clock jitter case, the BPD gain is constant for small DCO jitter and is inversely proportional to the square of jitter for large DCO jitter; in the latter case, the timing jitter has a normal-Laplace distribution.Index Terms-Bang-bang phase-locked loop, timing jitter, binary phase detector gain, asymptotic analysis.

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Section: Dbbpll Architecture and Modelmentioning

confidence: 99%

“…While they are typically implemented based on the charge-pump PLL architecture [2], [3], recent progress in the development of low-noise digitally-controlled oscillators (DCOs) has resulted in several digital BBPLL (DBBPLL) implementations suitable for high-bandwidth digital frequency synthesis [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

Tertinek

Gleeson

Feely

2010

IEEE Trans. Circuits Syst. II

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“…The ratio = / , called the stability factor 2 , is an important parameter in the loop design [1], as it determines performance metrics such as output jitter, loop stability and locking time. Note that assumption A1 implies that the stability factor is an integer satisfying > 1.…”

Section: D Mc Modelmentioning

confidence: 99%

“…While they are usually implemented based on the charge-pump architecture [2]- [4], the continuing trend to replace analog functions by digital blocks has resulted in digital BBPLL (DBBPLL) implementations suitable for high-bandwidth frequency synthesis [5]- [9]. A block diagram of a second-order DBBPLL is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Tertinek

Feely

2011

IEEE Trans. Circuits Syst. II

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“…In order to achieve stability in a bangbang PLL, the ratio of the proportional part to the integral part should be well defined [2]. Hence the first principle of parameter independence for a PLL in a bang-bang configuration can be stated as the following:…”

Section: Parameter Independent Loop Behaviormentioning

confidence: 99%

Analysis of parameter-independent PLLs with bang-bang phase-detectors

Toifl

Moreira²,

Marchioro³

et al.

1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.9

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The parameter-independent design of Phase-Locked Loops (PLLs) is investigated for the case that a bang-bang phase-detector is used. Two self-biased CMOS PLL structures are proposed and compared, one leading to a completely parameter-and frequency independent behavior. If the PLL frequency operation is constant and known in advance, however, both structures can be made independent of the transistor Vt and b parameters. AbstractThe parameter-independent design of Phase-Locked Loops (PLLs) is investigated for the case that a bangbang phase-detector is used. Two self-biased CMOS PLL structures are proposed and compared, one leading to a completely parameter-and frequency independent behavior. If the PLL frequency operation is constant and known in advance, however, both structures can be made independent of the transistor V t and b parameters.

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A two-chip 1.5-GBd serial link interface

Cited by 43 publications

References 3 publications

Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

Analysis of parameter-independent PLLs with bang-bang phase-detectors

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