A transaction-based unified architecture for simulation and emulation

Abstract

The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts. This paper describes a layered architecture suitable for both simulation and emulation. The architecture uses transactions for communication and synchronization between the driving environment (DE) and the device under test (DUT). Transactions provide synchronization only as needed and cycle and event-based synchronization common in emulators. The result is more efficient development of the DE and 100% portability when moving from simulation to emulation. We give an overview of our layered architecture and describe its implementation. Our results show that, by using emulation, the Register-Transfer level (RTL) implementation of an industrial design can be verified in the same amount of time it takes to run a C-based simulation. We also show two orders of magnitude speeds up over simulations of C and RTL through a programming language interface.

Internet-based multiuser in-circuit emulator design for 8051 microprocessors

“…Functional verification of such systems has been problematic [11]. Nowadays, the constant increase in the complexity of designs has led to functional testing to run application specific integrated circuits [9].…”

A novel methodology for hardware acceleration and emulation

“…Research found that the speed bottleneck of this methodology is mostly caused by the ping-pong mode of data transmission between workstation software and the FPGA emulator, thus resulting in that channel transmission time takes too much proportion of total time [1] [2]. In order to overcome the emulation channel transmission limits between workstations and FPGA, solutions are given by published papers [3][4][5][6][7][8][9].…”

Hierarchy Communication Channel in Transaction-Level Hardware/Software Co-emulation System

“…However, most of the research concentrates on methodology partitioning a system into transaction-level test, transactors and design [2], transaction-level modeling [3], development environment in system level [4], scheme for reducing communication traffic [5] without investigation on transaction-based architecture, especially from viewpoint of hierarchy architecture from bottom level to top level.…”