A tool for automatic generation of self-checking data paths

Hamdi, Belgacem; Bederr, H.; Nicolaidis, M.

doi:10.1109/vtest.1995.512675

Cited by 13 publications

(8 citation statements)

References 5 publications

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“…Related work on data path protection includes arithmetic and logic units protected with residue or parity codes [12]. Ernest et al [13] protects a CPU pipeline with razor which is a technique for timing error detection and correction.…”

Section: Related Workmentioning

confidence: 99%

A rapid prototyping system for error-resilient multi-processor systems-on-chip

May

Wehn

Bouajila

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only profitable if the costs in terms of area, energy and delay for reliability keep within limits. Therefore, the traditional worst case design methodology will become infeasible. Future architectures have to be error resilient, i.e., the hardware architecture has to tolerate autonomously transient errors.In this paper, we present an FPGA based rapid prototyping system for multi-processor systems-on-chip composed of autonomous hardware units for error-resilient processing and interconnect. This platform allows the fast architectural exploration of various error protection techniques under different failure rates on the microarchitectural level while keeping track of the system behavior. We demonstrate its applicability on a concrete wireless communication system.

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Section: Related Workmentioning

confidence: 99%

A rapid prototyping system for error-resilient multi-processor systems-on-chip

May

Wehn

Bouajila

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…Self-checking arithmetic operators based on arithmetic residue codes [Peterson and Weldon 1972], Berger codes [Lo et al 1992], and parity codes [Nicolaidis et al 1997] have been developed. CAD tools for automatic generation of generation of self-checking data paths [Hamdi et al 1995] and implementation of Berger code and parity code based CED during multi-level logic synthesis [De et al 1994] have also been developed.…”

Section: Related Researchmentioning

confidence: 99%

Introspection

Karri¹,

Iyer

2001

ACM Trans. Des. Autom. Electron. Syst.

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We report a register transfer level technique for concurrent error detection and diagnosis in data dominated designs called Introspection. Introspection uses idle computation cyles in the data path and idle data transfer cycles in the interconnection network in a synergistic fashion for concurrent error detection and diagnosis (CEDD). The resulting on-chip fault latencies are one ten-thousandth (10 −4 ) of previously reported system level concurrent error detection and diagnosis latencies. The associated area overhead and performance penalty are negligible. We derive a cost function that considers introspection constraints such as (i) executing an operation on three disjoint function units for diagnosis and (ii) promoting function units to participate in at least one CEDD operation. We formulate integration of introspection constraints into the operation-to-operator binding phase of high-level synthesis as a weighted bipartite matching problem. The effectiveness of introspection and its implementation are illustrated on numerous industrial strength benchmarks.

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“…This scheme detects the single errors produced on the outputs of the arithmetic unit. Parity prediction arithmetic units require the lower hardware overhead among all known self-checking arithmetic unit schemes [14], [16]. This scheme is compatible with parity checked data paths (which requires the minimum hardware overhead) and with parity encoded self-checking memory systems.…”

Section: Introductionmentioning

confidence: 99%

“…Parity prediction self-checking arithmetic units [16]- [18] and logic units [12] have also been proposed. This scheme detects the single errors produced on the outputs of the arithmetic unit.…”

Section: Introductionmentioning

confidence: 99%

Pass Transistor Based Self-Checking Full Adder

Hamdi¹,

Khedhiri²,

Rached³

2011

IJCTE

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Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage and reduced hardware cost with reduced design effort. The aim of this work is to contribute to reach these requirements for the design of self-checking adders/ALUs. In this paper, we present efficient self-checking implementations for adder schemes using the dual duplication code. Among the known self-checking adder designs, the dual duplicated scheme has the advantage to be totally self-checking for single faults. The drawback of this scheme is that it requires generally the maximum hardware overhead. In this work, we propose a low cost implementation for self-checking adder. The proposed design is based on a novel differential XOR gate implemented in CMOS pass transistor logic, and performed with only four transistors.

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A tool for automatic generation of self-checking data paths

Cited by 13 publications

References 5 publications

A rapid prototyping system for error-resilient multi-processor systems-on-chip

A rapid prototyping system for error-resilient multi-processor systems-on-chip

Introspection

Pass Transistor Based Self-Checking Full Adder

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