A timing methodology considering within-die clock skew variations

Sundareswaran, Savithri; Nechanicka, L.; Panda, Rajendran; Gavrilov, S. V.; Solovyev, Roman; Abraham, Jacob A.

doi:10.1109/socc.2008.4641543

Cited by 3 publications

(8 citation statements)

References 11 publications

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“…Another method for statistical clock skew analysis based on Monte Carlo simulation is introduced in [14]; the computational time of this method is, however, prohibitively high for large scale ICs. Several statistical skew modeling and timing analysis methods considering intra-die variations are presented in [13,15,16] to efficiently analyze skew variations. Although statistical skew analysis has been explored in 2-D ICs, the resulting methods cannot be directly applied to 3-D systems.…”

Section: Related Workmentioning

confidence: 99%

“…Since only the clock skew between the sequential elements which transfer data between each other (data-related sequential elements) affects the performance of a circuit [5,16], in addition to global skew, appropriate pair-wise skew distributions are adopted to evaluate the performance of clock distribution networks [16].…”

Section: Problem Descriptionmentioning

confidence: 99%

“…The fluctuation of the buffer delay is typically approximated as being linear to the device parameter variations [16,19]. Alternatively, the variation in delay can be determined through the variations of the input capacitance and output resistance [13].…”

Section: Buffer Delay Distributionmentioning

confidence: 99%

“…The systematic WID variations often exhibit spatial correlation [11,25], which can be modeled as a combination of multi-level random WID variations [25]. Consequently, a model for the random WID variations is utilized herein, following the methods used by other statistical skew analysis and process variation analysis papers [13,[15][16][17]. The validity of this approach is discussed and demonstrated in these publications.…”

Section: Wid Variation Model For the Delay Of 3-d Clock Pathsmentioning

confidence: 99%

“…In (16), all the random variables are equally affected by the D2D variations in plane j, which means that the correlation between every two variables is one. Since ∆d is also described by a Gaussian distribution,…”

Section: Skew Model Of 3-d Clock Trees With D2d Variationsmentioning

confidence: 99%

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Process-induced skew variation for scaled 2-D and 3-D ICs

Pavlidis

Micheli

2010

Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction

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Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented at scaled technology nodes and for a 3-D circuit with an increasing number of planes is investigated in this paper. An accurate model used to describe the effect of the proper sources of variations on each of these design approaches is proposed. The distribution of the pair-wise skew variation is obtained for single scaled or multi-plane (not scaled) clock distribution networks. The accuracy of the presented statistical skew model is verified through Monte-Carlo simulations. As shown in this paper, the clock skew variation due to technology scaling and/or die stacking exhibits a considerably different behavior. A comparison between these two design paradigms is offered such that the appropriate technology node and number of planes are selected to produce a low clock skew variation and high operating frequency. A popular global clock tree topology is employed in a planar (2-D) circuit where technology scaling is applied and in a 3-D circuit with an increasing number of planes. For this clock tree topology, the maximum supported clock frequency increases from 2.75 GHz to 3.74 GHz by proper die-stacking at a 90 nm technology node. 3-D integration is shown to be an alternative to reduce skew variation without the need of aggressive technology scaling.

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Section: Related Workmentioning

confidence: 99%

Section: Problem Descriptionmentioning

confidence: 99%

Section: Buffer Delay Distributionmentioning

confidence: 99%

Section: Wid Variation Model For the Delay Of 3-d Clock Pathsmentioning

confidence: 99%

Section: Skew Model Of 3-d Clock Trees With D2d Variationsmentioning

confidence: 99%

See 3 more Smart Citations

Process-induced skew variation for scaled 2-D and 3-D ICs

Pavlidis

Micheli

2010

Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction

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Development of a Method for Timing Analysis of Reconfigurable System-on-a-Chip Based on Models of Special Logic Elements

Telpukhov

Solovyev

Rukhlov

et al. 2020

2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)

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Effect of process variations in 3D global clock distribution networks

Pavlidis

Micheli

2012

J. Emerg. Technol. Comput. Syst.

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In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this article. A statistical clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D clock tree topologies are investigated and compared in terms of clock skew variation. The statistical skew model used to describe clock skew variations is verified through Monte-Carlo simulations. The clock skew is shown to change in different ways with the number of planes forming the 3D IC and the clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew. Tradeoffs between the investigated 3D clock distribution networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D clock trees is also compared with the skew variation of clock grids.

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A timing methodology considering within-die clock skew variations

Cited by 3 publications

References 11 publications

Process-induced skew variation for scaled 2-D and 3-D ICs

Process-induced skew variation for scaled 2-D and 3-D ICs

Development of a Method for Timing Analysis of Reconfigurable System-on-a-Chip Based on Models of Special Logic Elements

Effect of process variations in 3D global clock distribution networks

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