A Time Base Option for Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes

Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures

“…In the proposed system, the resampling algorithm receives, at any clock tick, a bunch of L samples, each one on 8 bits, where the clock rate is the one of the time-interleaved ADCs, i.e., f ck (period T ck ). The output is a version of the input signal resampled at a sample rate f s = C f ck , where the resampling factor C is an arbitrary (within the limits of the numeric precision detailed in Appendix II) fractional value in the interval [1/2, 1) selected by the user, [45]. It is produced as a sequence of valid bunches, which are saved in the acquisition memory, and invalid bunches that are instead discarded, thus lowering, as required, the sample rate.…”

“…The algorithm is illustrated in the following by firstly recalling the single channel algorithm presented in [45]- [47], and then detailing the operations of the multichannel algorithm that develop through three stages named: interpolation, defragmentation, and packing.…”

“…The proposal is inspired by a previous research work that led to the realization of a digital circuit capable of downsampling by a non-integer factor the stream of an individual channel at a maximum clock frequency up to a few GHz [45]- [47]. Such circuit uses a finite impulse response filter with dynamically varying coefficients and an effective strategy to occasionally discard samples for reducing the sample rate.…”

“…The proposed circuit exploits instead original approaches that allow: parallelizing the serial computation presented in [45]- [47]; distinguishing valid from dummy samples in the raw bunches collecting the time-interleaved ADCs outputs; defragmenting the raw bunches and compacting valid and invalid samples in separate bunches of fixed size; discarding the invalid bunches while saving the valid ones in the acquisition memory.…”

Digital Circuit for Seamless Resampling ADC Output Streams

“…A method that shows a viable solution to finely control the sampling rate in DSOs has been presented in Reference [19], and a digital circuit that implements this method using field programmable gate array (FPGA) technology has been illustrated at the ApplePies 2019 Conference [20]. In detail, the digital circuit exploits a resampling method based on linear interpolation, which trades-off between accuracy and circuit complexity.…”