A time A‐D converter LSI for accurate measurement of multitime‐interval by digital processing

Abstract

The authors previously have reported on the "ring gate delay" system which digitim the infinitesimal time interval with the delay time of the inverter as the resolution, without using the high-speed reference clock [ 11. A problem then is the improvement of the accuracy since the delay time of the inverter depends on various conditions such as the ambient temperature, the supply voltage, and the fabrication condition. To remedy this point, an LSI is constructed and the delay time of the original circuit is monitored continuously using the quartz oscillation clock of a relatively low frequency as the reference, and the time to be measured is digitized with a high accuracy based on the delay time. In this system, it is not necessary to control the delay time, which makes it possible to utilize the shortest delay time.By a single measurement process using a single input port, up to four pulses can be measured consecutively. If the pulse interval to be measured in less than the specified time, the pulses are combined into a single pulse and an incorrect operation is prevented.In this study, a sample device is constructed by a 1.5-pm CMOS process. The measurement range of 2200 ns (12 bit) with the time resolution 0.5 ns is achieved using the supply voltage of 5 V. The minimum pulse interval that can be measured is 55 ns (at 25°C). The reference clock used is 2 MHz. The number of transistors is 15,000 and the chip size is 3.5 mm X 3.8 mm. The constructed LSI is composed totally of digital circuits. The operation is robust against the environmental condition, and a stable operation is realized for the ambient temperature of -35 to 140°C.

Ultra‐low power digital front‐end for single lead ECG acquisition integrated with a time‐to‐digital converter

“…It can be calculated using (4) from the clock period and number of delay units . Traditional TDC architectures [15] employ synchronous counters and ‘always on’ latch enable signals that adversely affects the power of the design. It also causes clock loading effects.…”

A novel technique for improving temperature independency of ring-ADC

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