A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor

Tremblay, M.; Chaudhry, S.

doi:10.1109/isscc.2008.4523067

Cited by 102 publications

(64 citation statements)

References 3 publications

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“…Rock [102,18,23] is the first commercial processor that supports hardware transactional memory, and it implements a so called best effort hardware transactional memory. In order to support transactional memory, two new instructions have been added to the SPARC instruction set -chkpt and commit.…”

Section: Best Effort Hardware Transactional Memory In Rockmentioning

confidence: 99%

“…When the hardware resources are exhausted, HyTM switches to a software transactional memory implementation. HyTM has many similarities to Hybrid TM [53], NZTM [99,98], and the best effort hardware transactional memory in Rock [102,18,23]. HyTM provides a word-based interface to the transactional memory, in contrast to Hybrid TM and NZTM that rely on an object-based interface.…”

Section: Hybrid Transactional Memory Hytmmentioning

confidence: 99%

“…[99,98] relies on a best effort hardware transactional memory implementation. NZTM has many similarities to Hybrid TM [53], HyTM [21], and Rock [102,18,23]. When the hardware resources are exhausted, NZTM switches to a software transactional memory implementation.…”

Section: Phased Transactional Memory Phtmmentioning

confidence: 99%

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Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

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Section: Best Effort Hardware Transactional Memory In Rockmentioning

confidence: 99%

Section: Hybrid Transactional Memory Hytmmentioning

confidence: 99%

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Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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“…Most modern general purpose processors have several processing cores and, indeed, we can find processors with over 10 cores offered by several companies, such as the 10-core Intel Xeon processors [34], the 12-core AMD Opteron processors [15] or the 16-core Sparc processors [36], [38]. Even more processing cores are provided by the 48-core Larrabee processor from Intel [35] or the 64-core TILE64 processor offered by Tilera [9].…”

Section: Introductionmentioning

confidence: 99%

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Navaridas

Khan

et al. 2012

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

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Abstract-Architectural simulation is an essential tool when it comes to evaluating the design of future many-core chips. However, reproducing all the components of such complex systems precisely would require unreasonable amounts of computing power. Hence, a trade off between accuracy and compute time is needed. For this reason most state-of-the-art tools do not have accurate models for the networks-on-chip, and rely on timing models that permit fast-simulation. Generally, these models are very simplistic and disregard contention for the use of network resources. As the number of nodes in the network-on-chip grows, fluctuations with contention and other parameters can considerably affect the accuracy of such models. In this paper we present and evaluate a collection of timing models based on a reservation scheme which consider the contention for the use of network resources. These models provide results quickly while being more accurate than simple no-contention approaches.

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“…Hence hardware-assisted TM systems [2], [7], [23], where specialized hardware performs conflict detection and rollback, have been proposed. As an indication of the benefits of TM systems, Sun Microsystems has included support for transactional memory in its Rock processor [28].…”

Section: Introductionmentioning

confidence: 99%

Using hardware transactional memory for data race detection

Gupta

Sultan²,

Cadambi³

et al. 2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

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Abstract-Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable. Dependable multithreaded software will have to rely on the ability to dynamically detect nondeterministic and notoriously hard to reproduce synchronization bugs manifested through data races. Previous solutions to dynamic data race detection have required specialized hardware, at additional power, design and area costs. We propose RaceTM, a novel approach to data race detection that exploits hardware that will likely be present in future multiprocessors, albeit for a different purpose. In particular, we show how emerging hardware support for transactional memory can be leveraged to aid data race detection. We propose the concept of lightweight debug transactions that exploit the conflict detection mechanisms of transactional memory systems to perform data race detection. We present a proof-of-concept simulation prototype, and evaluate it on data races injected into applications from the SPLASH-2 suite. Our experiments show that this technique is effective at discovering data races and has low performance overhead.

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A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor

Cited by 102 publications

References 3 publications

Transactional memory

Transactional memory

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Using hardware transactional memory for data race detection

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