A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing

Mashreghi-Moghadam, Parisa; Ould-Bachir, Tarek; Savaria, Yvon

doi:10.1109/iscas48785.2022.9937607

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…Therefore, more efficient designs are needed that strike a balance between latency and resource utilization. Compared to the works in [15][16][17][18][19][20], our single-block recursive layout results in lower resource consumption. By employing a protocol-agnostic generic architecture we eliminate the need for generating multi-level structured parsing units.…”

Section: Related Workmentioning

confidence: 93%

“…Currently, common FPGA-based solutions adopt a multi-stage pipeline architecture for packet parsing [ 15 , 16 , 17 , 18 , 19 , 20 , 21 ], this approach assigns a separate parsing module to each protocol layer or type, resulting in a significant hardware resource overhead. Moreover, it fails to support packet parsing beyond the limit of available parsing modules, thus limiting parsing flexibility.…”

Section: Introductionmentioning

confidence: 99%

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The Design of a Dynamic Configurable Packet Parser Based on FPGA

Sun

Guo

2023

Micromachines

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To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA. The architecture consists of three protocol analysis modules and a TCAM-SRAM. Latency is reduced by optimizing the state machine and parallel extraction matching. At the same time, we introduce the chain mapping idea and container concept to formulate the matching and extraction rules of table entries and enhance the extensibility of the parser. Furthermore, our system supports dynamic configuration through SDN control, allowing flexible adaptation to diverse scenarios. Our design has been verified and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 80 Gbps, with a maximum latency of only 36 nanoseconds for L4 protocol parsing.

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Section: Related Workmentioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

The Design of a Dynamic Configurable Packet Parser Based on FPGA

Sun

Guo

2023

Micromachines

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An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs

Mashreghi-Moghadam

Ould-Bachir²,

Savaria

2023

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

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PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA

Mashreghi-Moghadam,

Ould-Bachir,

Savaria

2024

Future Internet

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The increasing complexity of modern networks and their evolving needs demand flexible, high-performance packet processing solutions. The P4 language excels in specifying packet processing in software-defined networks (SDNs). Field-programmable gate arrays (FPGAs) are ideal for P4-based packet parsers due to their reconfigurability and ability to handle data transmitted at high speed. This paper introduces three FPGA-based P4-programmable packet parsing architectural designs that translate P4 specifications into adaptable hardware implementations called base, overlay, and pipeline, each optimized for different packet parsing performance. As modern network infrastructures evolve, the need for multi-tenant environments becomes increasingly critical. Multi-tenancy allows multiple independent users or organizations to share the same physical network resources while maintaining isolation and customized configurations. The rise of 5G and cloud computing has accelerated the demand for network slicing and virtualization technologies, enabling efficient resource allocation and management for multiple tenants. By leveraging P4-programmable packet parsers on FPGAs, our framework addresses these challenges by providing flexible and scalable solutions for multi-tenant network environments. The base parser offers a simple design for essential packet parsing, using minimal resources for high-speed processing. The overlay parser extends the base design for parallel processing, supporting various bus sizes and throughputs. The pipeline parser boosts throughput by segmenting parsing into multiple stages. The efficiency of the proposed approaches is evaluated through detailed resource consumption metrics measured on an Alveo U280 board, demonstrating throughputs of 15.2 Gb/s for the base design, 15.2 Gb/s to 64.42 Gb/s for the overlay design, and up to 282 Gb/s for the pipelined design. These results demonstrate a range of high performances across varying throughput requirements. The proposed approach utilizes a system that ensures low latency and high throughput that yields streaming packet parsers directly from P4 programs, supporting parsing graphs with up to seven transitioning nodes and four connections between nodes. The functionality of the parsers was tested on enterprise networks, a firewall, and a 5G Access Gateway Function graph.

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A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing

Cited by 3 publications

References 14 publications

The Design of a Dynamic Configurable Packet Parser Based on FPGA

The Design of a Dynamic Configurable Packet Parser Based on FPGA

An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs

PrismParser: A Framework for Implementing Efficient P4-Programmable Packet Parsers on FPGA

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