A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits

Abstract

As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.

La influencia del aprendizaje automático en el futuro del análisis de tiempo estático

“…El ATS funciona mediante la simulación del comportamiento del circuito utilizando modelos matemáticos para predecir los retardos de propagación de las señales a través de diversas rutas dentro del diseño. Este análisis considera factores como los retardos introducidos por las compuertas, los retardos de interconexión, variaciones de la señal de reloj y las variaciones ambientales para evaluar con precisión el rendimiento temporal del circuito (Muthukrishnan & Sathasivam, 2022). El proceso que sigue este análisis generalmente implica los siguientes pasos (Kaeslin, 2015): (1) Generación de la lista de redes: el diseño del circuito se representa como una lista de redes, que es una descripción de las interconexiones entre los diversos componentes (como compuertas, flip-flops e interconexiones) en el circuito.…”

Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects

“…As the FAST-based method is found optimal for SDD detection, the quality metric must also validate the same, i.e., the change in clock frequency must change the metric value. Different delay test quality metrics are discussed in detail in [26]. These metrics are broadly classified into two types: statistical and non-statistical.…”

Advanced Research in Electronics: The Perspective of Women

“…The works described up to now are all based on instrumentation, discrete components, sensors, and programmable devices, and finally, perfectly completing the electronics framework, in [5], a characteristic topic concerning integrated electronics is addressed. In [5], the authors review the effect and impact of small delay defects (SDD) and hidden delay (HDD) in logic circuits, due to the technology scaling down in VLSI circuits. This topic is of particular importance for industries that operate in the production of high-quality chips.…”

“…This topic is of particular importance for industries that operate in the production of high-quality chips. The review addressed in [5] can contribute to the VLSI testing industry for further progress as, although many effective techniques have been developed to detect most of the defects in chips, many test escapes still happen. The authors provided a deep insight for researchers in the field of VLSI testing by giving a brief overview of the state-of-the-art and a roadmap to further progress.…”