A Systematic Design Methodology for Low-Power NoCs

Reehal, Gursharan; Ismail, Mohammed

doi:10.1109/tvlsi.2013.2296742

Cited by 8 publications

(1 citation statement)

References 26 publications

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“…IV-B1c). Taking those various low-power design techniques into account, a systematic design methodology can be adopted to achieve low power performance at design time such as in the work reported in [97]. In such design methodologies, power and performance models such as in [98] play crucial role.…”

Section: B Power-efficient Hardware For Mixed Criticality Systemsmentioning

confidence: 99%

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Fakih

Lenz

Azkarate-Askasua

et al. 2017

Microprocessors and Microsystems

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With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

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Section: B Power-efficient Hardware For Mixed Criticality Systemsmentioning

confidence: 99%