A Systematic Approach to Correlation Analysis of In-Line Process Parameters for Process Variation Effect on Electrical Characteristic of 16-nm HKMG Bulk FinFET Devices

Su, Ping-Hsun; Li, Yiming

doi:10.1109/tsm.2016.2585129

Cited by 7 publications

(4 citation statements)

References 43 publications

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“…Based on the need to increase the drive current, the high-k gate dielectric in FinFET [14][15][16][17][18] is gradually applied to fit the requirement of HPC IC products. However, the manufacturing cost is very expensive.…”

Section: Resultsmentioning

confidence: 99%

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

Liaw

Liao

Wang

et al. 2017

Физика И Техника Полупроводников

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The length of Source/Drain (S/D) extension (L SDE ) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer L SDE pFinFET provides a larger series resistance and degrades the drive current (I DS ), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter L SDE plus the shorter channel length demonstrates a higher trans-conductance (Gm) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer L SDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current.

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Section: Resultsmentioning

confidence: 99%

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

Liaw

Liao

Wang

et al. 2017

Физика И Техника Полупроводников

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“…The dependency of θ is denoted by the θ subscript (e.g., m θ ). The first and second terms in (12) refer to model accuracy and complexity. The third term corresponds to the likelihood tendency over the observation number, M [16].…”

Section: ) Gaussian Process Regressionmentioning

confidence: 99%

“…When d− → ∞, the BLR converges to the GPR. The BLR is trained by maximizing the type-II likelihood, as explained in ( 11)- (12).…”

Section: ) Bayesian Linear Regressionmentioning

confidence: 99%

Bayesian Optimization of MOSFET Devices Using Effective Stopping Condition

Kim

Shin

2021

IEEE Access

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Current nanometer-scale metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit short-channel, quantum, and self-heating effects, making modeling and analysis very complex. A few recent works have employed machine-learning (ML) techniques and neural networks (NN) to model the complex relationships and optimize devices, but a problem with the NN-based device optimization is that it is data-intensive. Bayesian optimization (BO) can realize ML-based data-efficient optimization of the MOSFET device, as it finds the global optimum while requiring few training data. BO stops theoretically when every candidate is explored, so previous works used a fixed number of iterations for the stopping condition. Such an empirical stopping condition is detrimental to the efficiency and reliability of BO, because the global optimum can be found at an earlier stage or even after stopping. Recently, maximum expected improvement (EI max ) with a tiny constant has been proposed as a stopping condition for BO. However, there have not been sufficient works for improving efficiency of BO. By advancing the EI max scheme, we have systemically investigated the effective stopping condition (ESC) for BO of MOSFET devices to boost the efficiency and reliability of optimization. We found that EI max less than a 1% of unit value was an efficient and reliable ESC for optimization, which resulted in upto-87.6% and up-to-47% reductions of required training data compared with the fixed iteration method and the tiny constant method, respectively. Our study provides a novel method to boost efficiency and reliability of BOs for the optimization of MOSFET design in the semiconductor industry.

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“…Among these variations, source/drain (S/D) process variations should be carefully controlled because those are directly related to source-to-drain leakage current as well as drive current. So far, several studies about the impacts of the S/D process variations on the Si-FinFETs including S/D epitaxy shape, depth [17]- [19], S/D length [20], [21], and S/D doping concentration [22] were addressed, but the studies on the vertically stacked Si-NSFETs were rarely reported.…”

Section: Introductionmentioning

confidence: 99%

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

et al. 2020

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Excess source and drain (S/D) recess depth (T SD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (I off , I on) in three-stacked NS channels and parasitic bottom transistor (tr pbt), gate capacitance (C gg), intrinsic switching delay time (τ d), and static power dissipation (P static) are investigated quantitatively according to the T SD variations. More S/D dopants diffuse into the tr pbt with the deeper T SD , so the I off and I on increase due to raised current flowing through the tr pbt. Especially, the I off of PFETs remarkably increases above the certain T SD (T SD,critical) compared to NFETs. Furthermore, the I on contribution of each channels having the T SD,critical is the largest at the top NS channel and the tr pbt has the ignorable I on contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) I on contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The C gg also increases with the deeper T SD by increasing parasitic capacitance, but fortunately, the τ d decreases simultaneously due to the larger increasing rate of the I on than that of the C gg for all SoC applications. However, the P static enormously increases with the deeper T SD , and low power application is the most sensitive to the T SD variations among the SoC applications. Comprehensive analysis of the inevitable tr pbt effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.

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A Systematic Approach to Correlation Analysis of In-Line Process Parameters for Process Variation Effect on Electrical Characteristic of 16-nm HKMG Bulk FinFET Devices

Cited by 7 publications

References 43 publications

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

Bayesian Optimization of MOSFET Devices Using Effective Stopping Condition

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

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