A system architecture exploration on the configurable HW/SW co-design for H.264 video decoder

Jian, Guo-An; Chu, Jui-Chin; Huang, Ting-Yu; Chang, Tao-Cheng; Guo, Jiun-In

doi:10.1109/iscas.2009.5118243

Cited by 9 publications

(6 citation statements)

References 10 publications

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“…In the context of embedded image processing, a homogeneous solution based on general-purpose processors would be too expensive and inefficient, while applicationspecific integrated circuits (ASICs) exhibit very good performance, but are too specialized and lack flexibility. A heterogeneous platform integrated in a SoC comprising both specialized hardware accelerators and general-purpose processors is therefore a widely accepted solution [9,14,28].…”

Section: Computing Environmentmentioning

confidence: 99%

List Scheduling in Embedded Systems Under Memory Constraints

Arras

Fuin

Jeannot

et al. 2014

Int J Parallel Prog

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Section: Computing Environmentmentioning

confidence: 99%

List Scheduling in Embedded Systems Under Memory Constraints

Arras

Fuin

Jeannot

et al. 2014

Int J Parallel Prog

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“…When the block size is 16 × 16, the repetitive redundant data are nearly twice the size of the necessary data. Thus, the VBSMC scheme [31] was proposed to fetch reference data in units of 21 × 21, 21 × 13, 13 × 21, 13 × 13, 13 × 9, 9 × 13, and 9 × 9 pixels for 16 × In order to take full advantage of the four RCAs in RPU, a 'Hybrid VBSMC' scheme is implemented to achieve a trade-off between memory bandwidth and calculation parallelism. Partitions with luma block sizes of 16 × 16, 16 × 8, 8 × 16 samples are divided into multiple 8 × 8 blocks to use 8 × 8 block-based MC.…”

Section: Mapping Strategy Of MC Onto Remus-iimentioning

confidence: 99%

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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“…A heterogeneous platform integrated in a SoC comprising both specialized hardware accelerators and general-purpose processors is therefore a widely accepted solution [7], [8], [19].…”

Section: A Computing Environmentmentioning

confidence: 99%

List Scheduling in Embedded Systems under Memory Constraints

Arras

Fuin

Jeannot

et al. 2013

2013 25th International Symposium on Computer Architecture and High Performance Computing

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International audienceVideo decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through appropriate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20\% can be achieved. Lastly, we show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics.Le décodage vidéo et le traitement d'image dans les systèmes embarqués sont sujets à de fortes contraintes de ressources, particulièrement en termes de mémoire. Les heuristiques d'ordonnancement de liste à priorités statiques (HEFT, SDC,...) étant les solutions les plus souvent citées en raison à la fois de leurs bonnes performances et de leur faible complexité, nous proposons une méthode visant à y introduire la notion de mémoire. De plus, nous montrons que par le biais d'un ajustement adapté des priorités des tâches et d'un recours judicieux à l'insertion, des accélérations jusqu'à 20% peuvent être obtenues. Enfin, nous montrons que notre technique permet d'empêcher les interblocages et de réduire significativement l'empreinte mémoire requise comparé à des heuristiques d'ordonnancement de liste classiques

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A system architecture exploration on the configurable HW/SW co-design for H.264 video decoder

Cited by 9 publications

References 10 publications

List Scheduling in Embedded Systems Under Memory Constraints

List Scheduling in Embedded Systems Under Memory Constraints

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

List Scheduling in Embedded Systems under Memory Constraints

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