A synthesizable IP core for WiMedia 1.5 UWB LDPC code decoding

Alles, Matthias; Wehn, Norbert; Berens, F.

doi:10.1109/icuwb.2009.5288833

Cited by 13 publications

(4 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The WiMedia standard [48] requires very high throughput: the work by Alles et al [29] manages to deliver more than 1 Gb/s throughputs for most code lengths and rates. The result is achieved via the instantiation of 3 PEs with VLSI Design 9 internal parallelism of 30: the similarity of WiMedia codes with the QC-LDPC of WiMAX allows a multiple submatrixlevel parallelism in the decoder.…”

Section: Designmentioning

confidence: 99%

Flexible LDPC Decoder Architectures

Awais

Condo

2012

VLSI Design

View full text Add to dashboard Cite

Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

show abstract

Section: Designmentioning

confidence: 99%

Flexible LDPC Decoder Architectures

Awais

Condo

2012

VLSI Design

View full text Add to dashboard Cite

show abstract

“…The first decoder we present makes use of a low-parallel hardware mapping and is designed for a WiMedia 1.5 based code. The architecture uses the concepts presented in [16], it is shown in Figure 7. Each set of 30 variable nodes is attributed to one of the three slots.…”

Section: Decoder Architecturesmentioning

confidence: 99%

Design Space of Flexible Multigigabit LDPC Decoders

et al. 2012

Self Cite

View full text Add to dashboard Cite

Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput while supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design space for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware is investigated in depth. Two new decoder architectures in a 65 nm CMOS technology are presented to further explore the design space. In the past, the memory domination was the bottleneck for throughputs of up to 1 Gbit/s. Our systematic investigation of column-versus row-based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The evolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state-of-the-art decoders. Slot 0Slot 1

show abstract

“…• An LDPC decoder which is WiMedia 1.5 compliant and optimized for throughput, supporting code rates from R=1/2-4/5 with two block lengths N=1200 and N=1320 bits [13].…”

Section: Assessment Of Metricsmentioning

confidence: 99%

“…A throughput of 960 Mbit/s at code rate R = 0.75 was defined in the standard. A code/architecture co-design approach [13] resulted in an LDPC decoder which has a much higher efficiency than the flexible LDPC decoder. Note that its efficiency is lower in both dimensions compared to a convolutional decoder.…”

Section: A Implementation Driven Design Space Explorationmentioning

confidence: 99%

On Complexity, Energy- and Implementation-Efficiency of Channel Decoders

Kienle

Wehn

Meyr

2011

IEEE Trans. Commun.

Self Cite

View full text Add to dashboard Cite

Future wireless communication systems require efficient and flexible baseband receivers. Meaningful efficiency metrics are key for design space exploration to quantify the algorithmic and the implementation complexity of a receiver. Most of the current established efficiency metrics are based on counting operations, thus neglecting important issues like data and storage complexity.In this paper we introduce suitable energy and area efficiency metrics which resolve the afore-mentioned disadvantages. These are decoded information bit per energy and throughput per area unit. Efficiency metrics are assessed by various implementations of turbo decoders, LDPC decoders and convolutional decoders. New exploration methodologies are presented, which permit an appropriate benchmarking of implementation efficiency, communications performance, and flexibility trade-offs. These exploration methodologies are based on efficiency trajectories rather than a single snapshot metric as done in state-of-the-art approaches. Index TermsChannel coding, algorithmic complexity, energy efficiency, design space exploration, design methodology. I. MOTIVATIONToday, high-end smart phones have to support multiple radio standards, advanced graphic-and media applications and many other applications resulting in a workload of about 100 giga operations per second in a power budget of 1 Watt [1]. The baseband processing in the radio part (mainly front-end processing, demodulation and decoding) requires more than 50% of the overall workload in a state-of-the-art 3.5G smart phone. To achieve higher spectral efficiency new transmission techniques like MIMO will be established. However, this will increase the workload even further. Thus there is a strong need for efficient wireless baseband receivers. The overall efficiency of a baseband receiver depends on • communications efficiency: expressed by the spectral efficiency and signal-to-noise ratio (SNR). The requirements on the communications efficiency have the largest impact on the selected baseband processing algorithms.

show abstract

A synthesizable IP core for WiMedia 1.5 UWB LDPC code decoding

Cited by 13 publications

References 10 publications

Flexible LDPC Decoder Architectures

Flexible LDPC Decoder Architectures

Design Space of Flexible Multigigabit LDPC Decoders

On Complexity, Energy- and Implementation-Efficiency of Channel Decoders

Contact Info

Product

Resources

About