A synthesis environment for designing DSP systems

Casavant, Albert E.; d'Abreu, M.; Dragomirecky, M.; Duff, Dave; Jasica, J.R.; Hartman, Michael J.; Hwang, Ki Soo; Smith, Wayne D.

doi:10.1109/54.19133

Cited by 38 publications

(8 citation statements)

References 7 publications

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“…In (Casavant et al, 1989) the circuit to be synthesized is described with a combination of algorithmic and structural level code and then the PARSIFAL tool synthesizes the code into a bit-serial DSP circuit implementation. The PARSIFAL tool is part of a larger E-CAD system called FACE and which included the FACE design representation and design manager core.…”

Section: Early High-level Synthesismentioning

confidence: 99%

High-Level Synthesis for Embedded Systems

Dossis¹

2012

Embedded Systems - Theory and Design Methodology

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Section: Early High-level Synthesismentioning

confidence: 99%

High-Level Synthesis for Embedded Systems

Dossis¹

2012

Embedded Systems - Theory and Design Methodology

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“…Using proprietary specification formats, and targeting specific applications domain (e.g. DSP) or hardware architecture templates is found in [4], [5], and [6]. High-level synthesis tasks such as the scheduling optimizations have been studied in [1], [7], [8], [9].…”

Section: Related Workmentioning

confidence: 99%

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs

Dossis¹

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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Abstract-High-level synthesis has been envisaged as a suitable methodology to design and deliver on time, at least large parts of today's complex IC systems. This paper describes a unified and integrated HLS framework, to automatically produce custom and massively-parallel hardware, including its memory and system interfaces from high-level sequential program code. Using compiler-generators and logic programming techniques, provably-correct hardware compilation flow is achieved. The utilized hardware optimization inference engine is driven by a set of resource constraints, which limit to a certain boundary the number of available hardware operators to function in parallel during each control step. This optimization reduces drastically the number of different control steps (states) of the implemented application. The hardware compilation runs are completed in orders-of-magnitude less time than that which would be needed by even very experienced HDL designers to implement the same applications in RTL code. Implementation results from synthesis of a number of control-dominated, linear and repetitive, applications including a MPEG video compression engine with up to a few hundred states, are presented. In all cases the HLS framework delivers quickly provably-correct, implementable RTL code and the optimized schedule is reduced at up to 30% in comparison with the initial schedule.

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“…This is in contrast with low sampling frequency applications where the number of different frequencies is much lower and where executions that correspond to different frequencies take place sequentially. This is usually done using a microcoded approach with loops to model different frequencies ( [13], [14], [15], [16], [17] (a) shows an implementation without changing the loop hierarchy of the specification 9 (b) shows an implementation with overlapping loop executions.…”

Section: High Throughput Dsp Applicationsmentioning

confidence: 99%

“…Most target architectures for DSP synthesis use a microcoded architecture ( [13], [14], [15], [16], [17]). Such architectures use a limited number of programmable arithmetic building blocks such as an ALU with 32 different instructions, a multiplier and a limited number of memories (RAM and/or ROM).…”

Section: Architecturementioning

confidence: 99%

PHIDEO: High-level synthesis for high throughput applications

Meerbergen

Lippens

Verhaegh

et al. 1995

Journal of VLSI Signal Processing

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Abstract.This paper describes a new approach to high-level synthesis for high throughput applications. Such applications are typically found in real-time video systems such as HDTV. The method is capable of dealing with hierarchical flow graphs containing loops with manifest boundaries and linear index expressions. The algorithm is based on the model of periodic operations which allows optimizations across loop boundaries. Processing units and storage units are minimized simultaneously. The algorithm is implemented in the PHIDEO system. The major parts of this system are the processing unit synthesis, the scheduler and the memory synthesis including address generation.

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A synthesis environment for designing DSP systems

Cited by 38 publications

References 7 publications

High-Level Synthesis for Embedded Systems

High-Level Synthesis for Embedded Systems

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs

PHIDEO: High-level synthesis for high throughput applications

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