A Survey of Machine Learning for Computer Architecture and Systems

Wu, Nan; Xie, Yuan

doi:10.1145/3494523

Cited by 92 publications

(11 citation statements)

References 222 publications

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“…But lately, reinforcement learning (RL) and machine learning methods have been applied to multicore systems, which have demonstrated favorable performance compared to alternative methods [18]. Isci et al proposed MaxBIPS, which thoroughly searches for the optimum combination of V/F levels that maximizes the performance due to the power constraint.…”

Section: B Power Managementmentioning

confidence: 99%

Performance Improvement of Processor Through Configurable Approximate Arithmetic Units in Multicore Systems

Gharavi,

Safari

2024

IEEE Access

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Multicore systems are utilized in a wide range of applications, from embedded systems to highperformance applications. Controlling power consumption while maximizing performance under the Thermal Design Power (TDP) becomes increasingly important when power density emerges as the key restriction for multicore systems. Dynamic voltage-frequency scaling (DVFS) approaches have been effective in dynamically power control and are commercially accessible. We propose a novel approach to improve the performance of multicore systems by utilizing configurable approximate Arithmetic units. The proposed system includes a machine learning-based framework for online power regulation and quality monitoring of application output. This framework dynamically adjusts the frequency and precision of the Arithmetic units to maximize performance while considering TDP constraints and the desired output quality. The experimental results demonstrate the effectiveness of the proposed approach. Using a floating point approximate Arithmetic Logic Unit (ALU) with three distinct configurations in each core, the multicore system can execute approximable applications up to 19% faster than a precise multicore system, while operating within the same TDP limit. INDEX TERMSApproximate computing, Reconfigurable approximate design, Computer architecture, Machine learning.

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Section: B Power Managementmentioning

confidence: 99%

Performance Improvement of Processor Through Configurable Approximate Arithmetic Units in Multicore Systems

Gharavi,

Safari

2024

IEEE Access

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“…LeaFTL applies learning techniques to optimize the address mapping. However, unlike existing optimizations [43,63] such as learned page table for virtual memory that used deep neural networks to learn the patterns, LeaFTL provides a lightweight solution. SSD Hardware Development.…”

Section: Related Workmentioning

confidence: 99%

LeaFTL: A Learning-Based Flash Translation Layer for Solid-State Drives

Sun¹,

Li²,

Sun³

et al. 2023

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems,

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In modern solid-state drives (SSDs), the indexing of flash pages is a critical component in their storage controllers. It not only affects the data access performance, but also determines the efficiency of the precious in-device DRAM resource. A variety of address mapping schemes and optimizations have been proposed. However, most of them were developed with human-driven heuristics.In this paper, we present a learning-based flash translation layer (FTL), named LeaFTL, which learns the address mapping to tolerate dynamic data access patterns via linear regression at runtime. By grouping a large set of mapping entries into a learned segment, it significantly reduces the memory footprint of the address mapping table, which further benefits the data caching in SSD controllers. LeaFTL also employs various optimization techniques, including out-of-band metadata verification to tolerate mispredictions, optimized flash allocation, and dynamic compaction of learned index segments. We implement LeaFTL with both a validated SSD simulator and a real open-channel SSD board. Our evaluation with various storage workloads demonstrates that LeaFTL saves the memory consumption of the mapping table by 2.9× and improves the storage performance by 1.4× on average, in comparison with state-of-the-art FTL schemes.

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“…A few recent reviews relate EDA in general and ML. Wu [37] presents an extensive study on the relation of ML techniques utilization on system modeling and computer architecture. In Khailany [38], a brief review of specific implementations from NVIDIA research members is presented.…”

Section: Machine Learning and Logic Synthesismentioning

confidence: 99%

Review of Machine Learning in Logic Synthesis

Berndt

Fogaça

Meinhardt

2022

JICS

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Electronic design automation tools have multiple options that need to be tuned for specific designs and technology nodes. Traditionally, the tuning process is done by teams of expert engineers and demands a large amount of computational resources.In recent years, there has been an increased effort to apply machine learning techniques in electronic design automation problems, attempting to increase the design flow correlation and predictability, hence reducing the time spent on tuning.In this work, we revise modern approaches in electronic design automation and machine learning techniques applied during logic synthesis. We categorize and discuss their core technologies, such as transforming data into images. Machine learning techniques are as good as the available data. Thus, we present existing learning datasets for logic synthesis and strategies such as data augmentation to overcome the lack of specific data for logic synthesis problems.To cope with these problems, we discuss how research is shifting from traditional supervised learning techniques to reinforcement learning-based methods.

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A Survey of Machine Learning for Computer Architecture and Systems

Cited by 92 publications

References 222 publications

Performance Improvement of Processor Through Configurable Approximate Arithmetic Units in Multicore Systems

Performance Improvement of Processor Through Configurable Approximate Arithmetic Units in Multicore Systems

LeaFTL: A Learning-Based Flash Translation Layer for Solid-State Drives

Review of Machine Learning in Logic Synthesis

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