A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing

Daoud, Luka; Zydek, Dawid; Selvaraj, Henry

doi:10.1007/978-3-319-01857-7_47

Cited by 41 publications

(24 citation statements)

References 26 publications

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“…Other high level languages can be used as input to HLS tools such as Java, Python, OpenCL, and CUDA. A survey on HLS models can be found in [48].…”

Section: Designing Custom Acceleratorsmentioning

confidence: 99%

Hardware accelerator design for data centers

Yesil¹,

Özdal²,

Ayupov³

et al. 2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized applicationspecific accelerators are becoming integral parts of modern system on chip (SOC) architectures. In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs.

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“…Other high level languages can be used as input to HLS tools such as Java, Python, OpenCL, and CUDA. A survey on HLS models can be found in [48].…”

Section: Designing Custom Acceleratorsmentioning

confidence: 99%

Hardware accelerator design for data centers

Yesil¹,

Özdal²,

Ayupov³

et al. 2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Obtaining an optimal scheduling in BSV can sometimes require some extra effort from the designer, due to the strict sequentially consistent paradigm of the language, which might not be obvious to designers with module mkSorter (SortBox#(n,t) [2], &temp [3]); compAndSwap(&temp [4], &temp [5]); compAndSwap(&temp [6], &temp [7]); ... an RTL background. Although Bluespec adopts many syntax expressions from SystemVerilog, the learning curve is steep even for developers with background in hardware design.…”

Section: A Bluespec Systemverilogmentioning

confidence: 99%

“…An exhaustive survey of HLS tools has been published recently by Daoud et al [7], describing a plethora of HLS tools from the last 30 years, but it does not provide any empirical evaluation or comparison between them. Bacon et al 's classification of HLS frameworks [6] is also very rich in technical details, but no direct comparison is made between different implementations.…”

Section: Related Workmentioning

confidence: 99%

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An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

Arcas-Abella

Ndu

Sönmez

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such as area and throughput, as well as on programmer experience.In this paper, we explore the different trade-offs present when using a representative set of HLS tools in the context of Database Management Systems (DBMS) acceleration. More specifically, we conduct an empirical analysis of four representative frameworks (Bluespec SystemVerilog, Altera OpenCL, LegUp and Chisel) that we utilize to accelerate commonly-used database algorithms such as sorting, the median operator, and hash joins. Through our implementation experience and empirical results for database acceleration, we conclude that the selection of the most suitable HLS depends on a set of orthogonal characteristics, which we highlight for each HLS framework.

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“…FPGAs are hardware reconfigurable computing tools that are suitable to design applications that are frequently upgraded during runtime. Applications can be wiritten in high level language and synthesised in FPGAs [1] that make them popular and easier to implment. FPGAs become more and more popular in the distributed computing [2], where system nodes contain FPGAs and are able to program them according to current needs [3].…”

Section: Introductionmentioning

confidence: 99%

A Survey on Design and Implementation of Floating Point Adder in FPGA

Daoud

Zydek

Selvaraj

2015

Progress in Systems Engineering

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Field Programmable Gate Arrays (FPGAs) are increasingly being used for high performance applications. FPGAs adopt such applications that require high numerical stability and accuracy. [7]. Most of numerical applications demand high level of accuracy in their calculations, and wide range of numbers. Floating point format satisfies such requirements. It has a wide range of numbers that can be presented with the fixed number of bits. Hence, most of applications implemented in FPGAs are represented in floating point format. In FPGAs, performance and area are the main issues to design efficient floating point units. Some compromises must be found between speed, accuracy, and the FPGA resources.

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A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing

Cited by 41 publications

References 26 publications

Hardware accelerator design for data centers

Hardware accelerator design for data centers

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

A Survey on Design and Implementation of Floating Point Adder in FPGA

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