A Survey on Design and Implementation of Floating Point Adder in FPGA

Abstract

Field Programmable Gate Arrays (FPGAs) are increasingly being used for high performance applications. FPGAs adopt such applications that require high numerical stability and accuracy. [7]. Most of numerical applications demand high level of accuracy in their calculations, and wide range of numbers. Floating point format satisfies such requirements. It has a wide range of numbers that can be presented with the fixed number of bits. Hence, most of applications implemented in FPGAs are represented in floating point format. In FPGAs, performance and area are the main issues to design efficient floating point units. Some compromises must be found between speed, accuracy, and the FPGA resources.

Acceleration System for Single-Precision Floating-Point Arithmetic Based on IEEE754 Standard

“…Overflow judgement judges the overflow situation by detecting the exponent and the mantissa of the sum. If the exponent of the sum is all 1, then it is overflow, output overflow=2'b01; If the exponent of the sum is all 0, and the mantissa of the sum is not all 0, then the result is a subnormal number, output overflow=2'b10; When the sum's exponent and mantissa are both in the normal number range, output overflow=2'b00 [11].…”

“…Floating-point numbers can be broadly categorized into single-precision, double-precision, and extended double-precision types, with bit widths of 32, 64, and over 80 bits respectively. Although a larger bit width theoretically promises enhanced arithmetic precision, it also necessitates greater storage and computational resources, potentially exacerbating data error probabilities [2]. Given these considerations, for small to mediumscale FPGA designs, single-precision floating-point numbers predominantly suffice.…”

A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching

“…Each descriptor is composed of 128 elements and its location, (x, y), in the image. Although each element should be represented as a doubleprecision floating-point to increase the accuracy, such floating-point adder circuits [17] is more complicated and consumes more resources. Therefore, for further optimization, each element of the descriptor is represented as a 16-bit fixed-point value and a total of 32-bits for its location, leading to an individual descriptor size of 2080 bits.…”