A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement

Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

“…This is mitigated by the SR enhancer that allows the settling time to follow the single-pole limit up to 0.9 V, also in this case. The plot shows also the single-pole limit evaluated using (22) with (9).…”

“…In the last 15 years, the extending demand for circuits with fast response to step inputs (i.e., discrete-time or switched-capacitor circuits, data converters, voltage regulators, etc.) has pushed the scientific community towards the design and the optimization of the settling time in low-voltage and multistage CMOS OTAs [9][10][11][12][13][14][15][16][17][18][19]. A significant number of design procedures have been proposed.…”

“…Figure 14.Settling time versus output step amplitude for the closed-loop amplifier compensated with the RNMC-ICBFF. The plot shows also the single-pole limit evaluated using(22) with(9).…”

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

“…Because of its wide knowledge and diffusion, we focus our attention on the three-stage OTA based on the reverse nested Miller compensation with a feed-forward stage (RNMC-FF) and to the case of large capacitive loads. Differently from the past works reported in the literature [37][38][39][40][41][42][43][44][45][46][47][48][49], the proposed design strategy (a) optimizes the speed/dissipation of the amplifier taking into account the settling time and the slewrate effects; (b) despite being developed for large capacitive loads, it also holds for lowcapacitive loads; and (c) despite being developed for the transistors biased in the subthreshold region, it also holds for the saturation one.…”