A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates

Son, Hwa–Young; Jung, Gi-Jo; Park, Byung-Jin; Paik, Kyung‐Wook

doi:10.1007/s11664-008-0498-0

Cited by 16 publications

(6 citation statements)

References 7 publications

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“…A Cu pillar with a thin solder cap structure, where bump bridging does not occur due to the small amount of solder used compared with conventional solder bumps, has recently been developed as a fine-pitch flip-chip packaging alternative. [4][5][6] Electrical reliability issues can also be solved with this structure because Cu pillars have superior electric conductivity. However, brittle Cu-Sn intermetallic compounds (IMCs) form at the joints in Cu pillar bumps because Cu atoms react with Sn atoms in the solder.…”

Section: Introductionmentioning

confidence: 99%

Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps

Lim

Kim

Lee³

et al. 2009

Journal of Elec Materi

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The in situ intermetallic compound (IMC) growth in Cu pillar/Sn bumps was investigated by isothermal annealing at 120°C, 150°C, and 180°C using an in situ scanning electron microscope. Only the Cu 6 Sn 5 phase formed at the interface between the Cu pillar and Sn during the reflow process. The Cu 3 Sn phase formed and grew at the interfaces between the Cu pillar and Cu 6 Sn 5 with increased annealing time. Total (Cu 6 Sn 5 + Cu 3 Sn) IMC thickness increased linearly with the square root of annealing time. The growth slopes of total IMC decreased after 240 h at 150°C and 60 h at 180°C, due to the fact that the Cu 6 Sn 5 phase transforms to the Cu 3 Sn phase when all of the remaining Sn phase in the Cu pillar bump is completely exhausted. The complete consumption time of the Sn phase at 180°C was shorter than that at 150°C. The apparent activation energy for total IMC growth was determined to be 0.57 eV.

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Section: Introductionmentioning

confidence: 99%

Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps

Lim

Kim

Lee³

et al. 2009

Journal of Elec Materi

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“…Due to tremendous effort of many research organizations and industries, state-of-art TSV forming and copper via filling can be successfully developed. As TSV vertical interconnection methods, Cu pillar/Sn-Ag bump structure is being widely investigated for 3D TSV chip stacking [2][3][4][5][6][7][8]. Recently, 40 lm pitch TSV-chip stacking is being applied in real products in IBM, Xillinx, Samsung, etc., however, there are two major problems in Cu pillar/ Sn-Ag bonding.…”

Section: Introductionmentioning

confidence: 99%

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40μm pitch Cu-pillar/Sn–Ag bump interconnection

Shin

Kim

Choi

et al. 2015

Microelectronics Reliability

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“…Therefore, a new shape for the bump structure is necessary to address this limitation. Cu/Sn micro-bumps are known to be one of the most promising candidates for the fine pitch interconnection materials in wafer level packaging because they do not cause bump bridging between adjacent bumps and uniform current distribution (Son, Jung, Park, and Paik, 2008). Electrical reliability issues can also be solved with this structure because Cu pillars have superior electric conductivity.…”

Section: Introductionmentioning

confidence: 99%

ELECTRICAL RELIABILITY OF Cu/Sn MICRO-BUMP IN WAFER LEVEL PACKAGING FOR BioMEMS DEVICES

Jeong¹,

Kim²,

Kwak³

et al. 2011

Proceedings of the International Conference on Biomedical Electronics and Devices

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The electrical reliability of Cu/Sn micro-bump in wafer level packaging for advanced BioMEMS devices applications were systematically investigated during current stressing condition. After bump bonding, Cu 3 Sn and Cu 6 Sn 5 intermetallic phases were observed, and Cu 3 Sn formed and grew at Cu pillar/Cu 6 Sn 5 interface with increasing annealing and current stressing time. The kinetics of intermetallic compound growth changed when all Sn in Cu/Sn micro-bump was exhausted. The complete consumption time of Sn phase in electromigration condition was faster than that in annealing condition. Under current stressing condition, intermetallic compound growth was significantly enhanced by current stressing where the growth rate follows a linear relationship with stressing time.

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A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates

Cited by 16 publications

References 7 publications

Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps

Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps

Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40μm pitch Cu-pillar/Sn–Ag bump interconnection

ELECTRICAL RELIABILITY OF Cu/Sn MICRO-BUMP IN WAFER LEVEL PACKAGING FOR BioMEMS DEVICES

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