A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process

Tsui, Bing-Yue; Tsai, Tsung-Che; Lu, Yulan; Lin, Jianyu; Hung, Che Lun; Wen, Y. X.

doi:10.1109/ted.2021.3120707

Cited by 7 publications

(2 citation statements)

References 23 publications

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“…The defective layer underneath FOX also has several benefits. It increases the V th value of the FOX MOSFET without field implantation 19 and reduces dopant encroachment, which can cause V th shift on narrow devices. 20 Dual gate oxidation with a compromised gate dielectric.-Certain CMOS circuits, such as level shifters, must operate at two voltages to convert a low input voltage to a high output voltage.…”

Section: Methodsmentioning

confidence: 99%

Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

Hung¹,

Tsui²,

Tsai³

et al. 2022

ECS J. Solid State Sci. Technol.

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In this study, the performance of complementary metal–oxide–semiconductor (MOS) circuits fabricated on SiC substrates was investigated by designing several digital and analog circuits, and a unique process flow was developed to integrate n-type MOS (NMOS) and p-type MOS (PMOS) transistors with low and high threshold voltages (Vth) into a single chip. A detailed process flow with local oxidation of SiC isolation and a dual gate oxide with a compromised gate dielectric are presented. The performance of NMOS field-effect transistors (FETs) and PMOSFETs with low and high Vth were characterized in detail. Lateral MOS capacitors were also fabricated in the same chip to explore the characteristics of the gate dielectric. Several common logic gate components were fabricated and tested at elevated temperatures to demonstrate the normal function of these elements in a digital circuit. Static random-access memory (SRAM) cells were designed and optimized through simulation. Characterizations of all the circuit blocks are presented to demonstrate the capability of these circuits in harsh environments.

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Section: Methodsmentioning

confidence: 99%

Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

Hung¹,

Tsui²,

Tsai³

et al. 2022

ECS J. Solid State Sci. Technol.

Self Cite

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“…Well and source/drain regions were then formed with Al and P ion implantations at 500 ℃, followed by a dopant activation annealing at 1700 °C for 30 min with carbon cap in Ar ambient. For device isolation, we employed LOCOSiC isolation structure through Ar ion implantation and a wet oxidation at 1100 °C for 5 hr [15,16]. The gate oxide was grown by wet oxidation at 1200 ℃ for 30 min followed by two kinds of POA process: pure (non-diluted) NO annealing or N2-diluted NO annealing at 1200 ℃ for 15 min.…”

Section: Experimental Conditionsmentioning

confidence: 99%

Bias-Induced Instability of 4H-SiC CMOS

Wen

Tsui

2023

MSF

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4H-SiC complementary metal-oxide-semiconductor (CMOS) devices for control circuit applications have been reported extensively, however, the electrical stability, even with interface optimization processes, degrades significantly after bias stress. In this paper, we performed both positive and negative bias stress on planar SiC NMOSFETs and PMOSFETs fabricated with pure (non-diluted) and N2-diluted NO post-oxidation annealing (POA) processes. The test results indicate the existence of positive hole traps might be the culprit that leads to electrical characteristics instability during operation and pure NO annealing is effective to reduce the instability.

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Cristobalite formation on high-temperature oxidation of 4H-SiC surface based on silicon atom sublimation

Wei,

Li,

Zhao

et al. 2024

Materials Today Communications

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A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process

Cited by 7 publications

References 23 publications

Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

Bias-Induced Instability of 4H-SiC CMOS

Cristobalite formation on high-temperature oxidation of 4H-SiC surface based on silicon atom sublimation

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