A Study on Optimal Scheduling Using High-Bandwidth Memory of Knights Landing Processor

Rho, Seungwoo; Park, Geunchul; Kim, Jik-Soo; Kim, Seo Young; Nam, Dukyun

doi:10.1109/fas-w.2017.161

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…Overall, Phi does not provide comparable performance to CPU as a stand-alone shared memory processor. Thread-affinity strategy Balanced, 4,14,20,21,23,26,36 scatter, 37 compact, 92 no single winner 13,84,94 Memory mode Cache, 60,62 flat, 55,90,96 hybrid (none), no single winner [10][11][12]52,54,57,97 Interconnect clustering mode All-to-all (none), quadrant, 11,62 sub-NUMA, 10,55,57,96,97 no single winner 52,96…”

Section: Gaining Insights Into Phi Architecturementioning

confidence: 99%

A survey on evaluating and optimizing performance of Intel Xeon Phi

Mittal

2020

Concurrency and Computation

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Summary Intel's Xeon Phi combines the parallel processing power of a many‐core accelerator with the programming ease of CPUs. In this paper, we present a survey of works that study the architecture of Phi and use it as an accelerator for a broad range of applications. We review performance optimization strategies as well as the factors that bottleneck the performance of Phi. We also review works that perform comparison or collaborative execution of Phi with CPUs and GPUs. This paper will be useful for researchers and developers in the area of computer‐architecture and high‐performance computing.

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Section: Gaining Insights Into Phi Architecturementioning

confidence: 99%

A survey on evaluating and optimizing performance of Intel Xeon Phi

Mittal

2020

Concurrency and Computation

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Towards optimal scheduling policy for heterogeneous memory architecture in many-core system

et al. 2018

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Simulating the Network Activity of Modern Manycores

2019

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Manycore architectures are one of the most promising candidates to reach the exascale. However, the increase in the number of cores on a single die exacerbates the memory wall problem. Modern manycore architectures integrate increasingly complex and heterogeneous memory systems to work around the memory bottleneck while increasing computational power. The Intel Mesh Interconnect architecture is the latest interconnect designed by Intel for its HPC product lines. Processors are organized in a rectangular network-on-chip (NoC), connected to several different memory interfaces, and using a distributed directory to guarantee coherent memory accesses. Since the traffic on the NoC is completely opaque to the programmer, simulation tools are needed to understand the performance trade-offs of code optimizations. Recently featured in Intel's Xeon Scalable lines, this interconnect was first included in the Knights Landing (KNL), a manycore processor with up to 72 cores. This work analyzes the behavior of the Intel Mesh Interconnect through the KNL architecture, proposing ways to discover the physical layout of its logical components. We have designed and developed an extension to the Tejas memory system simulator to replicate and study the low-level data traffic of the processor network. The reliability and accuracy of the proposed simulator is assessed using several state-of-the-art sequential and parallel benchmarks, and a particular Intel Mesh Interconnect-focused locality optimization is proposed and studied using the simulator and a real KNL system.

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A Study on Optimal Scheduling Using High-Bandwidth Memory of Knights Landing Processor

Cited by 3 publications

References 5 publications

A survey on evaluating and optimizing performance of Intel Xeon Phi

A survey on evaluating and optimizing performance of Intel Xeon Phi

Towards optimal scheduling policy for heterogeneous memory architecture in many-core system

Simulating the Network Activity of Modern Manycores

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