A Study of the Electroforming Process in 1T1R Memory Arrays

Abstract

For reproducible resistive switching in memristive devices, electroforming is a crucial process. However, a deeper understanding of the electroforming process is still lacking due to unavailability of a proper simulation tool. Here, we propose a physics-based compact model for the electroforming of valence change mechanism (VCM) memristive devices. The developed JART VCM Forming model is experimentally validated with ZrOx based memristive device. Further, the electroforming process in different 1T1R memristive arrays is simulated with this model. The study shows that the electrical characteristics of each device in the array after the forming process is influenced by word/bit line series resistance. In addition, control effects depending on the channel width and applied gate voltage of transistor in the 1T1R cell are also investigated with the compact model simulation.