A Study of Outlier Analysis Techniques for Delay Testing

Wu, Shaomin; Drmanac, Dragoljub; Wang, Li-C.

doi:10.1109/test.2008.4700548

Cited by 25 publications

(8 citation statements)

References 28 publications

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“…This paper can be seen as an extension of the outlier delaytest methodology proposed in [4], where it was shown that One-Class SVM outlier analysis is an effective method for accurately detecting subtle delay defects while minimizing the number of overkills. Although the proposed methodology was capable of detecting 70-80% of all delay defects, it did so at a huge test cost, requiring thousands of transition fault patterns and a large number of test clocks.…”

Section: Related Workmentioning

confidence: 99%

“…In [6] and [7] all measurements are compared collectively as a current signature, analogous to the delay-test signature used in [4], which was found to be more robust than individual comparisons. A different data representation is used in [8], where the author proposes detecting outliers using current ratios between a samples minimum and maximum measurement.…”

Section: Related Workmentioning

confidence: 99%

“…To perform SVM learning an appropriate feature representation and similarity metric are required. We use the delay-test signature feature representation and the angle similar measure proposed by [4].…”

Section: Svm Outlier Analysismentioning

confidence: 99%

“…To test chips manufactured by processes with significant variations, a methodology designed to deal with variability is needed. The authors in [4] show that One-Class Support Vector Machine (SVM) outlier analysis is an effective approach for detecting subtle delay defects when analyzing delay-test data; however, they do not consider the test application cost. In this work, we aim to apply One-Class SVM outlier analysis to detect chips with small delay defects (outliers) in the presence of both systematic and random process variations while minimizing the cost of applying such a test.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Minimizing outlier delay test cost in the presence of systematic variability

Drmanac

Bolin

Wang

et al. 2009

2009 International Test Conference

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This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while information content measurements guide test clock selection. Exhaustive simulation found tradeoffs between reducing the number of clocks, patterns, and chip samples. Substantial cost reduction was obtained with proper clock selection, while minimizing both test patterns and circuit samples required for effective outlier analysis.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Svm Outlier Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Minimizing outlier delay test cost in the presence of systematic variability

Drmanac

Bolin

Wang

et al. 2009

2009 International Test Conference

View full text Add to dashboard Cite

show abstract

“…Learning a model for a single class of samples is a 1-class unsupervised learning problem and we can use the 1-class SVM algorithm to solve the problem. The 1-class SVM algorithm was studied extensively in [7] before. Based on the 45 conformal samples from the first set of data, we applied 1-class SVM to build a model CM 45 ().…”

Section: Building a Conformal Modelmentioning

confidence: 99%

Data learning techniques and methodology for Fmax prediction

Chen

Wang

Chang

et al. 2009

2009 International Test Conference

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The question of whether or not structural test measurements can be used to predict functional or system Fmax, has been studied for many years. This paper presents a data learning approach to study the question. Given Fmax values and structural delay measurements on a set of sample chips, we propose a method called conformity check whose goal is to select a subset of conformal samples such that a more reliable predictor can be built on. Our predictor consists of two models, a conformal model that decides on a given chip if its Fmax is predictable or not, and a prediction model that outputs the predicted Fmax based on results obtained from structural test measurements. We explain the data learning methodology and study various data learning techniques using frequency data collected on a highperformance microprocessor design.

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Motion of an underwater self-reconfigurable robot with tree-like configurations

Wang

Zhuang

et al. 2013

J. Shanghai Jiaotong Univ. (Sci.)

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A Study of Outlier Analysis Techniques for Delay Testing

Cited by 25 publications

References 28 publications

Minimizing outlier delay test cost in the presence of systematic variability

Minimizing outlier delay test cost in the presence of systematic variability

Data learning techniques and methodology for Fmax prediction

Motion of an underwater self-reconfigurable robot with tree-like configurations

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