A Study of JK and T Flip Flops with and without Delay Using QCA

Abstract

As transistors decrease in size, more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The use of quantum dots instead of CMOS transistors for implementing digital system at nanolevel is becoming more and more popular because of its faster speed, smaller size and low power consumption. Many interesting QCA-based logic circuits with smaller feature size, higher operating frequency, and lower power consumption than CMOS have been presented, even though the design of logic modules in QCA is not always straightforward. In this paper, the basic sequential logic structures-JK and T flip-flops are discussed based on QCA design, with comparatively less number of cells and area. Such devices are expected to function with ultra low power consumption and very high speed. Along with it, a design for T flip-flop with a delay is compared with a T flip-flop without any delay. The simulation result clearly testifies the validity of T flip-flop with delay.