A study of DRAM failures in the field

Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory

“…Recent field studies of DRAM faults indicate that memory errors follow some idiosyncratic trends due to this structure [4,17,18,2,3]. Large-scale analyses of DRAM fault patterns in Jaguar (with DDR2) [2] and Cielo (with DDR3) [3] indicate that most faults are confined to a single DQ, owing to the subarray structure of DRAM. Bamboo ECC is well suited for correcting this important fault mode because of its vertical symbol layout.…”

“…We prefer SPC-TPD usage because it has a very high detection coverage, detecting 100% of up-to-3-pin errors and virtually all (99.9996%) errors beyond this point. The stronger correction capability of DPC, on the contrary, is less helpful as faults affecting exactly 2 pins are infrequent (a field measurement on 2-bit symbol correction [2] showed little improvement over SEC-DED) while it can increase the SDC probability by aggressively miscorrecting severe errors. SPC-TPD can be configured in a (64 + 4)-DQ configuration over a 64-bit data channel, halving the redundancy of SEC-DED (6.25% SPC misses some SEC-DED-correctable error patterns.…”

“…DRAM components may become more vulnerable to hard and intermittent faults as DRAM transistor dimensions and supply voltages decrease [1], leading to more permanent and repeated memory errors [2,3,4]. When also considering the growing number of memory parts in large systems and the high cost of replacing recently-introduced on-package stacked memories [5,6,7], it is clear that strong and long-lasting error protection for future memory systems is necessary.…”

“…Such schemes use error coding to allow for continuous operation despite the failure of one or two DRAM chips. Field analyses report that chipkill-correct significantly improves memory reliability by correcting 99.94% of all errors [11], achieving a 42× better uncorrected DRAM error rate than single-bit correction [2].…”

“…a subarray fault) or the DRAM external interface (e.g. a fault in a through-silicon-via [TSV]), (2) aligning ECC symbols to frequent error patterns allows more frequent corrections, (3) while an ECC code guarantees detec-tion of errors up to a certain severity, careful analysis reveals that some codes provide superior detection capabilities beyond these guarantees.…”