A Study of a Transactional Parallel Routing Algorithm

Watson, J. R.; Kirkham, Harold; Lujan,

doi:10.1109/pact.2007.4336228

Cited by 41 publications

(40 citation statements)

References 21 publications

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“…Previous work by Chandy, Kim et al [5] Some preliminary work has demonstrated the potential to optimistically parallelize CAD algorithms. Watson et al demonstrate the potential for using TM to parallelize Lee's routing algorithm through the use of a simulation of an abstracted TM system, analyzing the available parallelism and amount of work done [6]. They begin with a simple approach, and then adapt their parallel implementation further to achieve significantly more parallelism.…”

Section: Related Workmentioning

confidence: 99%

Parallelizing FPGA placement using Transactional Memory

Birk

Steffan

Anderson

2010

2010 International Conference on Field-Programmable Technology

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Abstract-To capitalize on the growing abundance of multicore hardware, FPGA vendors have begun to parallelize the most compute intensive algorithms in their CAD software. However, parallelization is a painstaking and hence expensive process that limits the number of algorithms that can be cost-effectively parallelized. Transactional Memory (TM) promises an easier-touse alternative to locks for critical sections in threaded codeallowing programmers to avoid deadlocks and data races, and also allowing critical sections to execute in parallel as long as they dynamically access independent data. In this paper, we present our work on using TM to parallelize simulated annealingbased placement for FPGAs. In particular, we use a software TM (TinySTM) to parallelize the placement phase of Versatile Place and Route (VPR) 5.0.2 [1]. With TM we very quickly produced a parallel and correct version of the software, allowing us to focus on incrementally tuning performance. We describe our experiences in tuning the TM system and CAD software, and the interesting algorithmic trade-offs that exist. In the end, we found that optimized transactional placement has the potential for scalable performance: our non-deterministic implementation achieves self-relative speedups over a single thread of 1.82x, 3.62x and 7.27x at 2, 4, and 8 threads respectively with little quality degradation. However, hardware support for TM is likely required to overcome the overheads of STM, as our implementation's single thread performance is 8x slower than sequential VPR.

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Section: Related Workmentioning

confidence: 99%

Parallelizing FPGA placement using Transactional Memory

Birk

Steffan

Anderson

2010

2010 International Conference on Field-Programmable Technology

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“…The only difference is that modified locations in memory are tracked manually, rather than being automatically handled by the platform. Since only a tiny fraction of the memory accessed by the algorithm can cause dependencies, this is also more efficient, as others have found in similar physical design problems (for example, Watson et al [2007]). …”

Section: The Dependency Checkermentioning

confidence: 85%

Efficient and Deterministic Parallel Placement for FPGAs

Ludwin

Betz

2011

ACM Trans. Des. Autom. Electron. Syst.

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We describe a parallel simulated annealing algorithm for FPGA placement. The algorithm proposes and evaluates multiple moves in parallel, and has been incorporated into Altera's Quartus II CAD system. Across a set of 18 industrial benchmark circuits, we achieve geometric average speedups during the quench of 2.7x and 4.0x on four and eight processors, respectively, with individual circuits achieving speedups of up to 3.6x and 5.9x. Over the course of the entire anneal, we achieve speedups of up to 2.8x and 3.7x, with geometric average speedups of 2.1x and 2.4x.Our algorithm is the first parallel placer to optimize for criteria other than wirelength, such as critical path length, and is one of the few deterministic parallel placement algorithms. We discuss the challenges involved in combining these two features and the new techniques we used to overcome them. We also quantify the impact of maintaining determinism on eight cores, and find that while it reduces performance by approximately 15% relative to an ideal speedup of 8.0x, hardware limitations are a larger factor and reduce performance by 30-40%. We then suggest possible enhancements to allow our approach to scale to 16 cores and beyond.

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“…Labyrinth implements a variant of Lee's algorithm [12]: For each pair of input points, the program finds the shortest route that connects them in a three-dimensional uniform grid that represents the maze. The main transaction of the program encloses the calculation of the path and its addition to the global grid.…”

Section: Emulating Early Release: Genome and Labyrinthmentioning

confidence: 99%

Hardware transactional memory with software-defined conflicts

Titos-Gil

Acacio

Garcia

et al. 2012

ACM Trans. Archit. Code Optim.

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In this paper we propose conflict-defined blocks, a programming language construct that allows programmers to change the concept of conflict from one transaction to another, or even throughout the course of the same transaction. Defining conflicts in software makes possible the removal of dependencies which, though not necessary for the correct execution of the transactions, arise as a result of the coarse synchronization style encouraged by TM. Programmers take advantage of their knowledge about the problem and specify through confict-defined blocks what types of dependencies are superfluous in a certain part of the transaction, in order to extract more performance out of coarse-grained transactions without having to write minimally synchronized code. Our experiments with several transactional benchmarks reveal that using software-defined conflicts, the programmer achieves significant reductions in the number of aborted transactions and improve scalability.1

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A Study of a Transactional Parallel Routing Algorithm

Cited by 41 publications

References 21 publications

Parallelizing FPGA placement using Transactional Memory

Parallelizing FPGA placement using Transactional Memory

Efficient and Deterministic Parallel Placement for FPGAs

Hardware transactional memory with software-defined conflicts

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