A star network approach in heterogeneous multiprocessors system on chip

Wang, Chao; Li, Xi; Zhang, Junneng; Zhou, Xuehai; Wang, Aili

doi:10.1007/s11227-012-0810-x

Cited by 17 publications

(3 citation statements)

References 19 publications

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“…Kshitij Sudan reduces page size to enhance memory access efficiency in [19]. Works to reduce the DRMA latency are also carried out in [2], [12], [14], [15], [16], [18]. But all of these researches treat Kernel's accesses and User's accesses equally.…”

Section: Related Workmentioning

confidence: 99%

Kernel-User Space Separation in DRAM Memory

Sun

Zhu

et al. 2014

2014 IEEE International Symposium on Parallel and Distributed Processing With Applications

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Performance of software is increasingly restricted by the Memory Wall instead of CPU. Many studies focus on alleviating the DRAM latency by improving the row-buffer hit rate. But most of them treat the Kernel 1 and User 2 equally. Data used by Operating System and User applications spread in different rows of the same bank, leading to the contentions for the row-buffer when they access the bank successively. We find that contentions between Kernel and User make up of a great proportion of all the row-buffer misses. To alleviate the contentions between Kernel and User, we divide the united DRAM memory space into Kernel-Space and User-Space. A new page-allocation-system, the K/U-Aware page-allocation-system, is proposed to manage Kernel-Space and User-Space in DRAM memory in different address mapping schemes of DRAM memory controller. In the new system, pages are allocated from different spaces according to applicants (Kernel or User). Sizes of the two spaces increase and decrease dynamically as required. For benchmarks in PARSEC suites, the proposed system reduces the contentions of Kernel and User effectively, producing significant improvements of row-buffer hit rate. The execution time is reduced by 9.45% (max. 20.45%) and 6.51% (max. 18.05%) respectively in two typical address mapping schemes.

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Section: Related Workmentioning

confidence: 99%

Kernel-User Space Separation in DRAM Memory

Sun

Zhu

et al. 2014

2014 IEEE International Symposium on Parallel and Distributed Processing With Applications

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“…8. The framework communicates with other parts with a FIFO interface, which is adaptive for different data amount and transfer rate [11]. Numeric on the lines indicates the data width of the signals.…”

Section: B Hardware Platformmentioning

confidence: 99%

Multi-objective aware design flow for coarse-grained systems on chip

Chen

Wang

et al. 2014

2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications

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This paper presents a software and hardware codesign flow for the coarse-grained systems on chip. It enables a multi-target design space exploration (MT-DSE) algorithm with multiple objectives such as chip area utilization, energy consumption, core efficiency, interconnection structure, application workload and speedup aware. With the help of the MT-DSE tool, the proposed design flow can supply a valuable assistance for architecture designers to develop a well trade-off multi-processor system. In contrast, most of state-of-the-art design space exploration tools rely on varieties of simulations or implementations that are quite time-consuming. Benefit from no such dependences, the MT-DSE method could turn out the optimized alternative very fast with multiple factors balanced. Besides, the tool is employed at a very early stage in the component based systems design and only needs a little profiling information which can greatly reduce the development term of the design. As an illustration, the JPEG compression algorithm is chosen to demonstrate how the tool exploits a given application and guides to build the most desired architecture.

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“…We use Microblazes version 7.20.a as scheduling and computing processor, which are mentioned in section III. The experimental platform is extended from [24].…”

Section: A Experimental Setupmentioning

confidence: 99%

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

Guo

Wang

Zhou

et al. 2013

2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications

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Out-of-order execution scheme is one of the most promising technologies for task level parallelization in MPSoC design paradigms. However, it still poses a significant challenge to efficiently analyze the inter-task dependencies. This paper applies a traditional instruction level Scoreboarding algorithm at the task level in two forms: dynamic and static. A heterogeneous MPSoC prototype has been developed on FPGA with state-of-the-art dynamic partial reconfigurable technologies. The leverage between static and dynamic scheduling using task dependency analysis is obtained. Experimental results demonstrated a trade-off for the two modalities.

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A star network approach in heterogeneous multiprocessors system on chip

Cited by 17 publications

References 19 publications

Kernel-User Space Separation in DRAM Memory

Kernel-User Space Separation in DRAM Memory

Multi-objective aware design flow for coarse-grained systems on chip

Static or Dynamic: Trade-Offs for Task Dependency Analysis for Heterogeneous MPSoC

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