A standard cell approach for MagnetoElastic NML circuits

Giri, Davide; Vacca, Marco; Causapruno, Giovanni; Rao, Wenjing; Graziano, Mariagrazia; Zamboni, Maurizio

doi:10.1145/2770287.2770304

Cited by 5 publications

(2 citation statements)

References 15 publications

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“…When the electric field is removed, the shape anisotropy becomes predominant again and magnets switch to a stable state propagating the information. The complete theoretical analysis is reported in [21], while in [12] a possible fabrication process is described. The maximum clock frequency that can be used for NML circuits is limited by the time necessary to reset magnets and their successive switching.…”

Section: Magnetoelastic Clockmentioning

confidence: 99%

“…While the technological solution is similar to the one proposed in [20], our approach is technology-friendly, developed accordingly to current fabrication processes limitations. The particular circuits structure derived by this solution leads to the definition of a limited amount of possible basic structures, defined as "Standard Cells" [21] [12], that we adopt in this work. This predefined set of Standard Cells can be easily used to design circuits both with custom layout and using automated tools [22][23] [24] greatly enhancing the development of NML technology.…”

Section: Introductionmentioning

confidence: 99%

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Modeling, Design, and Analysis of MagnetoElastic NML Circuits

Giri

Vacca

Causapruno

et al. 2016

IEEE Trans. Nanotechnology

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With the predicted end of CMOS scaling process, researchers started to study several alternative technologies. Among them NanoMagnet Logic (NML) offers advantages complementary to MOS transistors especially for its magnetic nature. Its intrinsic memory capability makes it suitable for zero stand-by power and logic-in-memory applications. NML requires a clock system that, if based on a magnetic field, highly increases the circuit dynamic power consumption. We have recently proposed a solution based on the magnetoelastic effect (ME-NML) [1] and on currently available fabrication processes, which drastically reduces dynamic power consumption. However, many questions still remain unanswered. Which kind of applications are best suited for this technology? How can we effectively design, analyze and compare ME-NML circuits? Does it really offer advantages over state-of-the-art CMOS transistors? In this paper we provide answers to all these questions and the results prove that this technology offers indeed extremely good performance. We have designed a Galois Field Multiplier with a systolic array structure to reduce interconnection overhead. We developed a new RTL model that allows us to easily describe and simulate circuits of any complexity, evaluating at the same time the performance and keeping into account technology constraints. We approach for the first time in the NML scenario the design of ME-NML circuits adopting the standardcell method used in standard technologies and fulfill the design down to the physical level. The same circuit is designed also with NML technology based on magnetic fields and with a 28 nm low power CMOS bulk technology for comparison. The CMOS circuit is obtained through physical place&route with a commercial tool, providing therefore the most accurate comparison ever presented in literature. Power analysis shows that ME-NML circuits have a considerable advantage over both NML and state of the art CMOS bulk technology. As a further by-product results clearly highlight which kind of architectures can better exploit the true potential of NML technology.

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Section: Magnetoelastic Clockmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Modeling, Design, and Analysis of MagnetoElastic NML Circuits

Giri

Vacca

Causapruno

et al. 2016

IEEE Trans. Nanotechnology

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Logic-in-Memory architecture made real

Pala

Causapruno

Vacca

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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The current trend for intensive computational architectures is to adopt massive parallelism, with several concurrent tasks performed simultaneously, as done for example in GPUs. This approach has many advantages, such as the reduced design time given by circuit replication and an increasing in computational speed without the need of higher frequency. It has however evidenced an important bottleneck in data exchange between memory and processor.We envisage a revolutionary path for the future relation between memory and logic in parallel processors, where a new type of architecture exploits the principle of caching to the limit. Our Logic-in-Memory (LIM) architecture mixes logic and memory in the same device, removing the bottleneck of other existing parallel solutions. The architecture we propose, here in its preliminary version, has an array organization and each element in the array is based on three blocks: a logic unit for processing, a smart memory block and a routing structure for inter block communication. In this article we show the benefits of this approach with an application example in the image processing field. We can achieve a 4X computational time reduction for an image processing algorithm (Summed Area Table) with respect to the best architecture present in the literature, even with a preliminary and not optimized version.Besides the adoption of massive parallelism to increase performance, new technologies to open the post-CMOS era are explored. Among them NanoMagnet Logic (NML) is particularly interesting for its ability to mix logic and memory in the same device. We present here the preliminary results of the NML implementation of the LIM architecture. We thus demonstrate that it is not only a good solution for a standard CMOS technology but can also exploit the potential of an emerging technology as NML.

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